IP Library Granted Patent US 8,045,937
Granted Patent B2
US 8,045,937 · App. 12/251,169 · Granted Oct 25, 2011

Digital phase feedback for determining phase distortion

Assignee: Infineon Technologies AG
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Quick Facts
Patent No.
US 8,045,937
App. No.
12/251,169
Granted
Oct 25, 2011
Kind
B2
Abstract

A feedback loop is used to determine phase distortion created in a signal by directly extracting the phase distortion information from a feedback signal using original frequency modulation information.

Claims (32)

1. A circuit for determining a phase distortion comprising:

a phase modulator that receives a reference signal and a frequency modulation signal for generating a first signal;

a delay block that receives and delays the frequency modulation signal;

a Sigma-Delta modulator that receives the delayed frequency modulation signal for determining a corresponding divider ratio;

a multi-modulus divider that receives a feedback signal derived from the first signal and divides the feedback signal according to the divider ratio received from the Sigma-Delta modulator for removing phase modulation applied by the phase modulator; and

a time-to-digital converter for receiving the feedback signal output from the multi-modulus divider and the reference signal as inputs, and for outputting a derived signal representing phase distortion of the first signal.

2. The circuit according to claim 1 , further comprising:

a multiplier for multiplying the first signal with an amplitude modulation signal prior to deriving the feedback signal from the first signal; and

a phase restoration block that receives the feedback signal prior to the multi-modulus divider for restoring phase to the feedback signal.

3. The circuit according to claim 1 , further comprising a lowpass filter for receiving the derived signal representing phase distortion of the first signal and for removing noise added by the Sigma-Delta modulator.

4. The circuit according to claim 1 , wherein the delay block is an all-pass filter that delays the frequency modulation signal to match a delay in the feedback signal.

5. The circuit according to claim 1 , further comprising a directional coupler for receiving the first signal following modulation and from which the feedback signal is derived as a trace signal.

6. The circuit according to claim 1 , further comprising a reference clock for providing the reference signal to the phase modulator and for providing the reference signal to the time-to-digital converter.

7. The circuit according to claim 1 , wherein the derived signal that is output by the time-to-digital converter is a derived time difference representing phase distortion added to the first signal in a transmit path including the phase modulator.

8. The circuit according to claim 1 ,

wherein the phase modulator and a multiplier or a power amplifier make up a transmit path of the first signal, and

wherein phase distortion added to the feedback signal by a feedback path is small compared to phase distortion added to the first signal by the transmit path.

9. The circuit according to claim 2 , wherein the phase restoration block includes a signal limiter for removing amplitude information from the feedback signal.

10. The circuit according to claim 1 , wherein the multi-modulus divider removes the phase modulation applied by the phase modulator by dividing a frequency of the feedback signal according to the divider ratio received from the Sigma-Delta modulator to reduce the frequency of the feedback signal, whereby the phase modulation is removed.

11. The circuit according to claim 1 , wherein the derived signal is used for adaptive predistortion compensation for compensating for phase distortion in the first signal caused by a transmit path including the phase modulator.

12. A circuit for determining a phase distortion in a transmit path of a polar transmitter, comprising:

a reference clock for outputting a reference signal;

a phase modulator that receives the reference signal and a frequency modulation signal for generating a modulated first signal;

a multiplier that multiplies the modulated first signal with an amplitude modulation signal for producing a transmit signal, wherein the transmit path includes the phase modulator and the multiplier;

a coupler for deriving a feedback signal from the transmit signal;

a phase restoration block that receives the feedback signal and removes amplitude information therefrom;

a delay block that receives and delays the frequency modulation signal to match a delay in the feedback signal;

a Sigma-Delta modulator for receiving the delayed frequency modulation signal for determining a corresponding divider ratio;

a multi-modulus divider for receiving the feedback signal derived from the phase restoration block and dividing the feedback signal according to the divider ratio received from the Sigma-Delta modulator for removing phase modulation applied by the phase modulator; and

a time-to-digital converter for receiving the feedback signal from the multi-modulus divider and the reference signal as inputs and for outputting a derived representation of the phase distortion in form of a time delta.

13. The circuit according to claim 12 , wherein the time-to-digital converter outputs the time delta as a digital signal representing phase distortion caused by the transmit path of the first signal.

14. The circuit according to claim 12 , wherein the measured phase distortion signal is used for reducing transmit distortion and therefore improving spectral quality or other transmit parameter of said transmit path.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2012
From: INFINEON TECHNOLOGIES AG
To: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
Reel/Frame 027548/0623 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ADDRESS: THOMAS MAYER, INFINEON, BUCHNERSTRASSE 12, LINZ, AUSTRIA 4020 & NICK SHUTE, STRAUBIGNER STR. 5, MUNCHEN, GERMANY 80687 PREVIOUSLY RECORDED ON REEL 021818 FRAME 0447. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT ADDRESS: THOMAS MAYER, BUECHNERSTRASSE 12, 4020 LINZ, AUSTRIA & NICK SHUTE, STRAUBINGER STR. 5, 80687 MUENCHEN, GERMANY. Recorded Feb 12, 2009
From: MAYER, THOMAS; SHUTE, NICK
To: INFINEON TECHNOLOGIES AG
Reel/Frame 022260/0116 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2008
From: MAYER, THOMAS; SHUTE, NICK
To: INFINEON TECHNOLOGIES AG
Reel/Frame 021818/0447 →
Continuity (1)
Related Publication 20100091828A1 · Apr 15, 2010