Variable partitioning in a hybrid memory subsystem

1. A memory subsystem for use in a device, comprising:

volatile memory;

nonvolatile memory;

a first volatile memory interface to directly interface to volatile memory control, data, and address busses of the device;

a second volatile memory interface to directly interface to control, data, and address busses of the volatile memory;

the memory subsystem configured to present an exclusively volatile memory interface to the device;

logic to pass signals unchanged between the first volatile memory interface to the second volatile memory interface;

logic to make available to the device at least one first portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure, including unmodified areas in the first portion; and

logic to make available to the device at least one second portion of the volatile memory that can be modified by the device but that will not be backed up to the nonvolatile memory in the event of device power failure; and

logic to enable the device to configure the first and second portions.

2. The memory subsystem of claim 1 , further comprising:

one or more configuration registers to enable the device to configure the at least one first portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure.

3. A device comprising:

a memory subsystem comprising volatile memory, nonvolatile memory, and a first volatile memory interface to directly interface to volatile memory control, data, and address busses of the device, a second volatile memory interface to directly interface to control, data, and address busses of the volatile memory, and logic to pass signals unchanged between the first volatile memory interface to the second volatile memory interface;

the memory subsystem configured to present an exclusively volatile memory interface to the device;

logic to make available to the device at least one first portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure, including unmodified areas in the first portion; and

logic to make available to the device at least one second portion of the volatile memory that that can be modified by the device but that will not be backed up to the nonvolatile memory in the event of device power failure.

4. The device of claim 3 , the memory subsystem further comprising:

one or more configuration registers to enable the device to configure the at least one first memory portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure.

5. A method of operating memory in a device, comprising:

configuring at least one first register to define a first partition of volatile memory of a memory system of the device to be backed up to nonvolatile memory of the memory system in the event of device power failure, including unmodified areas of the first partition;

configuring at least one second partition of the volatile memory to be not backed up to the nonvolatile memory in the event of device power failure despite the contents of the second partition being modified by the device;

receiving data, address, and control information for the volatile memory directly from an internal memory bus of the device;

passing the received data, address, and control information unchanged through a controller to the volatile memory.

6. The method of claim 5 , further comprising:

configuring at least one second register to define a first partition of the nonvolatile memory to be not reserved for backups from the volatile memory.

7. A memory subsystem for use in a device, comprising:

volatile memory;

nonvolatile memory;

a first volatile memory interface to directly interface to volatile memory control, data, and address busses of the device;

a second volatile memory interface to directly interface to control, data, and address busses of the volatile memory;

logic to pass signals unchanged between the first volatile memory interface to the second volatile memory interface;

logic to make available to the device at least one first partition of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure, including unmodified areas of the first partition; and

logic to make available to the device at least one second partition of the volatile memory that will be not be backed up to the nonvolatile memory in the event of device power failure even when modified; and

logic to make available to the device at least one first partition of the nonvolatile memory that will not be used to back up the volatile memory in the event of device power failure.

8. The memory subsystem of claim 7 , further comprising:

one or more configuration registers to enable the device to define the at least one first partition of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure.

9. The memory subsystem of claim 7 , further comprising:

one or more configuration registers to enable the device to define the at least one first partition of the nonvolatile memory that is not reserved for backups from the volatile memory.

10. A device comprising:

a memory subsystem comprising volatile memory, nonvolatile memory, and

logic to make available to the device at least one first partition of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure, including unmodified areas of the first partition; and

logic to make available to the device at least one second partition of the volatile memory that will be not be backed up to the nonvolatile memory in the event of device power failure even when modified; and

logic to make available to the device at least one first partition of the nonvolatile memory that will not be used to back up the volatile memory in the event of device power failure

the memory subsystem comprising

a first volatile memory interface to directly interface to volatile memory control, data and address busses of the device;

a second volatile memory interface to directly interface to control, data, and address busses of the volatile memory; and

logic to pass signals unchanged between the first volatile memory interface to the second volatile memory interface.

11. The device of claim 10 , the memory subsystem further comprising:

one or more configuration registers to enable the device to define the at least one first partition of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure.

12. The device of claim 10 , the memory subsystem further comprising: one or more configuration registers to enable the device to specify the at least one first partition of the nonvolatile memory that is not reserved for backups from the volatile memory.

13. A method of operating memory in a device, comprising:

configuring at least one first partition of volatile memory of a memory system of the device to be backed up to nonvolatile memory of the memory system in the event of device power failure, including unmodified areas of the first partition;

configuring at least one second partition of the volatile memory to not be backed up to the nonvolatile memory in the event of device power failure even when modified;

configuring at least one third partition of the nonvolatile memory to not be used for backup of the volatile memory in the event of device power failure;

receiving data, address, and control information for the volatile memory directly from an internal memory bus of the device; and

passing the received data, address, and control information unchanged through a controller to the volatile memory.