Semiconductor device for improving the peak induced voltage in switching converter
A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.
1. A power semiconductor device, comprising:
a backside metal layer;
a substrate formed on the backside metal layer;
a semiconductor layer formed on the substrate, comprising:
a first trench structure comprising a first gate oxide layer formed around a first trench with poly-Si implant;
a second trench structure comprising a second gate oxide layer formed around a second trench with poly-Si implant;
a p-base region formed between the first trench structure and the second trench structure;
a plurality of n+ source regions formed on the p-base region and between the first trench structure and the second trench structure; and
a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source regions; and
a frontside metal region formed on the semiconductor layer and filling gaps formed between the plurality of n+ source regions on the p-base region, wherein the gaps are arranged in a chessboard form.
2. The power semiconductor device of claim 1 , wherein the first trench structure comprises a top end extension region extended from top end of the first trench to both sides of the first trench with poly-Si implant.
3. The power semiconductor device of claim 2 , wherein the gaps formed between the plurality of n+ source regions on the p-base region are separated from the top end extension region and not overlapped with the top end extension region.
4. The power semiconductor device of claim 1 , wherein the first trench structure comprises a plurality of top end extension regions extended from top end of the first trench to both sides of the first trench with poly-Si implant respectively.
5. The power semiconductor device of claim 4 , wherein the plurality of top end extension regions is formed on top of the first trench along a first direction alternately.
6. The power semiconductor device of claim 4 , wherein the plurality of top end extension regions is formed on top of the first trench symmetrically.
7. The power semiconductor device of claim 4 , wherein the plurality of top end extension regions is formed on top of the first trench asymmetrically.
8. The power semiconductor device of claim 4 , wherein the plurality of top end extension regions have the same shape.
9. The power semiconductor device of claim 4 , wherein the plurality of top end extension regions have different shapes.
10. The power semiconductor device of claim 4 , wherein the gaps formed between the plurality of n+ source regions on the p-base region are separated from the plurality of top end extension regions and not overlapped with the plurality of top end extension regions.
11. The power semiconductor device of claim 1 , wherein the gaps formed between the plurality of n+ source regions on the p-base region are arranged in a bar form.
12. The power semiconductor device of claim 1 , wherein each of the gaps formed between the plurality of n+ source regions on the p-base region comprises a p+ contact region.