Semiconductor wafer
A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation portion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.
1. A wafer comprising:
a substrate having a main surface and an undersurface oppositely positioned along a thickness direction;
an element that is formed on the main surface of the substrate and configures a semiconductor integrated circuit unit;
a through isolation portion formed by burying a first insulating film in a first trench provided from the main surface toward the undersurface of the substrate; and
a through interconnect portion that is formed by burying a conductive film in a second trench provided from the main surface toward the undersurface of the substrate within a region surrounded by the through isolation portion of the substrate, and is electrically connected to a semiconductor circuit unit of another wafer to be laminated;
wherein the through isolation portion and the through interconnect portion protrude from the undersurface of the substrate and are exposed.
2. The wafer according to claim 1 , wherein the wafer is a wafer of an intermediate layer of the plurality of wafers to be laminated, and a bump electrically connected to the semiconductor integrated circuit unit of the wafer of the intermediate layer is placed, as being exposed, on an uppermost layer of a main surface of the wafer of the intermediate layer.
3. The wafer according to claim 1 , wherein the wafer is a wafer of an uppermost layer of the plurality of wafers to be laminated, and an external terminal electrically connected to the semiconductor integrated circuit unit of the wafer of the uppermost layer is placed on an uppermost layer of the main surface of the wafer of the uppermost layer and the external terminal is placed in a state where it is exposed without a bump joined.