Semiconductor integrated circuit

1. A semiconductor integrated circuit comprising:

K number of memory cells coupled to a same word line;

a plurality of sense amplifier circuits coupled to the memory cells, wherein the plurality of sense amplifier circuits are divided into N number of groups,

K and N are natural numbers of 2 or more,

among the N number of groups, after a first group of sense amplifier circuits is activated and carrying out a predetermined read-out operation, a second group of the sense amplifier circuits is activated and the predetermined read-out operation is carried out, and

an Nth group of the sense amplifier circuits is activated sequentially to carry out the predetermined read-out operation;

an ECC circuit that inputs data read out from the N number of groups to carry out an ECC process; and

a parity bit cell for the ECC process, the parity bit cell being connected to the word line,

wherein

if K/N<2 x is satisfied, x+1 number of the parity bit cells are connected to each of the groups,

if 2 x <K/N<2 x+1 is satisfied, x+1 number of the parity bit cells are connected to N−1 number of groups among the groups and x+2 number of the parity bit cells are connected to a remaining one group, and

x is a positive integer.

2. A semiconductor integrated circuit, comprising:

a plurality of memory cells coupled to a selected word line;

a first sense amplifier group and a second sense amplifier group coupled to the memory cells; and

a control circuit coupled to the first and the second sense amplifier groups to control operation timing of the first and the second sense amplifier groups in response to the selected word line,

wherein the control circuit suspends an operation of the first sense amplifier groups no later than an activation of the second sense amplifier.

3. The semiconductor integrated circuit according to claim 2 , wherein the control circuit controls so that operation time of the sense amplifier in the first and the second sense amplifier groups is not overlapped.