Error recovery within processing stages of an integrated circuit
View Patent ↗An integrated circuit includes a plurality of processing stages each including processing logic 1014 , a non-delayed signal-capture element 1016 , a delayed signal-capture element 1018 and a comparator 1024 . The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014 . An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024 . The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
1. An integrated circuit comprising:
a plurality of processing stages forming a processing pipeline;
error detecting circuitry coupled to at least one of said plurality of processing stages and configured to detect an error in a processing operation of said at least one of said plurality of processing stages; and
clock phase control circuitry coupled to said at least one of said plurality of processing stages and to said error detecting circuitry and configured to be responsive to a detected error in operation of said at least one of said plurality of processing stages to phase shift an edge of a clock signal controlling operation of said at least one of said plurality of processing stages relative to another clock signal controlling at least one other processing stage of said processing pipeline so as to provide more time for said at least one of said plurality of processing stages to perform said processing operation.
2. An integrated circuit as claimed in claim 1 , wherein said clock phase control circuitry is configured to dynamically control said phase shift during ongoing operation of said apparatus.
3. An integrated circuit as claimed in claim 1 , wherein phase shifting said edge provides more time for said at least one of said plurality of processing stages to perform said processing operation and also provides less time for at least one further processing stage to perform its processing operation.
4. An integrated circuit as claimed in claim 1 , further comprising error recovery circuitry configured to be responsive to said error detection circuitry to enable said apparatus to recover from said detected error.
5. An integrated circuit comprising:
a plurality of processing stage means forming a processing pipeline means;
error detecting means coupled to at least one of said plurality of processing stage means for detecting an error in a processing operation of said at least one of said plurality of processing stage means; and
clock phase control means circuitry coupled to said at least one of said plurality of processing stage means and to said error detecting means and responsive to a detected error in operation of said at least one of said plurality of processing stage means to phase shift a clock edge of a clock signal controlling operation of said at least one of said plurality of processing stage means relative to another clock signal controlling at least one other processing stage means of said processing pipeline means so as to provide more time for said at least one of said plurality of processing stage means to perform said processing operation.
6. A method of operating an integrated circuit having a plurality of processing stages forming a processing pipeline, said method comprising the steps of:
detecting an error in a processing operation of at least one of said plurality of processing stages; and
phase shifting a clock edge of a clock signal controlling operation of said at least one of said plurality of processing stages relative to another clock signal controlling at least one other processing stage of said processing pipeline so as to provide more time for said at least one of said plurality of processing stages to perform said processing operation.
7. A method as claimed in claim 6 , wherein said phase shift is dynamically controlled during ongoing operation of said apparatus.
8. A method as claimed in claim 6 , wherein phase shifting of said edge provides more time for said at least one of said plurality of processing stages to perform said processing operation and also provides less time for at least one further processing stage to perform its processing operation.
9. A method as claimed in claim 6 , performing a recovery operation in response to said detected error to enable said apparatus to recover from said detected error.