Minimizing impact of design changes for integrated circuit designs

1. A method of updating an existing netlist to reflect a design change, the method comprising:

providing a register transfer level (RTL) design incorporating the design change to a synthesis tool;

providing the existing netlist to the synthesis tool;

setting the existing netlist to a read-only condition to prevent a change to the existing netlist;

synthesizing the design and the read-only existing netlist with the synthesis tool reusing logic structures from the read-only existing netlist by performing an optimization of the design and the read-only existing netlist with an objective to minimize the design space, the optimization being constrained by the read-only existing netlist; and

generating by the synthesis tool the existing read-only netlist and a portion of a new netlist reflecting the design change.

2. The method of claim 1 further comprising:

modifying the existing netlist with the portion of the new netlist reflecting the change.

3. The method of claim 2 wherein modifying the existing netlist comprises:

matching inputs and outputs of a portion of the existing netlist with the portion of the new netlist; and

replacing the portion of the existing netlist with the portion of the new netlist.

4. The method of claim 2 wherein the modification of the existing netlist is performed by the synthesis tool.

5. The method of claim 2 further comprising:

updating placement, routing, and timing using the modified netlist.

6. The method of claim 1 wherein the design is provided in the form of a netlist.