IP Library › Granted Patent US 8,069,393

Granted Patent B2

US 8,069,393 · App. 12/355,694 · Granted Nov 29, 2011

Method and system for providing long and short block length low density parity check (LDPC) codes

Assignee: DTVG Licensing, Inc.

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Quick Facts

Patent No.: US 8,069,393
App. No.: 12/355,694
Granted: Nov 29, 2011
Kind: B2

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Abstract

An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For 1/3 rate, the relevant parameters are as follows: q=120, n ldpc =64,800, k ldpc =n BCH =21600, k BCH =21408 (12 bit error correcting BCH). For 1/4 rate, the LDPC code has the following relevant parameters: q=135, n ldpc =64,800, k ldpc =n BCH =16200, k BCH =16008 (12 bit error correcting BCH). For 2/5 rate, the following parameters exist: q=108, n ldpc =64800, k ldpc =n BCH =25920, k BCH =25728 (12 bit error correcting BCH). The above approach has particular application in digital video broadcast services over satellite.

Claims (552)

1. A method comprising:

storing edge values used to compute parity check equations relating to Low Density Parity Check (LDPC) codes; and

decoding the LDPC codes based on the computed parity check equations, wherein the LDPC codes have one of a code rate of 1/3, a code rate of 1/4, or a code rate of 2/5 associated with respective tables each specifying addresses of parity bit accumulators,

Address of Parity Bit Accumulators (Rate ⅓)

34903 20927 32093 1052 25611 16093 16454 5520 506 37399 18518 21120

11636 14594 22158 14763 15333 6838 22222 37856 14985 31041 18704 32910

17449 1665 35639 16624 12867 12449 10241 11650 25622 34372 19878 26894

29235 19780 36056 20129 20029 5457 8157 35554 21237 7943 13873 14980

9912 7143 35911 12043 17360 37253 25588 11827 29152 21936 24125 40870

40701 36035 39556 12366 19946 29072 16365 35495 22686 11106 8756 34863

19165 15702 13536 40238 4465 40034 40590 37540 17162 1712 20577 14138

31338 19342 9301 39375 3211 1316 33409 28670 12282 6118 29236 35787

11504 30506 19558 5100 24188 24738 30397 33775 9699 6215 3397 37451

34689 23126 7571 1058 12127 27518 23064 11265 14867 30451 28289 2966

11660 15334 16867 15160 38343 3778 4265 39139 17293 26229 42604 13486

31497 1365 14828 7453 26350 41346 28643 23421 8354 16255 11055 24279

15687 12467 13906 5215 41328 23755 20800 6447 7970 2803 33262 39843

5363 22469 38091 28457 36696 34471 23619 2404 24229 41754 1297 18563

3673 39070 14480 30279 37483 7580 29519 30519 39831 20252 18132 20010

34386 7252 27526 12950 6875 43020 31566 39069 18985 15541 40020 16715

1721 37332 39953 17430 32134 29162 10490 12971 28581 29331 6489 35383

736 7022 42349 8783 6767 11871 21675 10325 11548 25978 431 24085

1925 10602 28585 12170 15156 34404 8351 13273 20208 5800 15367 21764

16279 37832 34792 21250 34192 7406 41488 18346 29227 26127 25493 7048

39948 28229 24899

17408 14274 38993

38774 15968 28459

41404 27249 27425

41229 6082 43114

13957 4979 40654

3093 3438 34992

34082 6172 28760

42210 34141 41021

14705 17783 10134

41755 39884 22773

14615 15593 1642

29111 37061 39860

9579 33552 633

12951 21137 39608

38244 27361 29417

2939 10172 36479

29094 5357 19224

9562 24436 28637

40177 2326 13504

6834 21583 42516

40651 42810 25709

31557 32138 38142

18624 41867 39296

37560 14295 16245

6821 21679 31570

25339 25083 22081

8047 697 35268

9884 17073 19995

26848 35245 8390

18658 16134 14807

12201 32944 5035

25236 1216 38986

42994 24782 8681

28321 4932 34249

4107 29382 32124

22157 2624 14468

38788 27081 7936

4368 26148 10578

25353 4122 39751

Address of Parity Bit Accumulators (Rate ¼)

23606 36098 1140 28859 18148 18510 6226 540 42014 20879 23802 47088

16419 24928 16609 17248 7693 24997 42587 16858 34921 21042 37024 20692

1874 40094 18704 14474 14004 11519 13106 28826 38669 22363 30255 31105

22254 40564 22645 22532 6134 9176 39998 23892 8937 15608 16854 31009

8037 40401 13550 19526 41902 28782 13304 32796 24679 27140 45980 10021

40540 44498 13911 22435 32701 18405 39929 25521 12497 9851 39223 34823

15233 45333 5041 44979 45710 42150 19416 1892 23121 15860 8832 10308

10468 44296 3611 1480 37581 32254 13817 6883 32892 40258 46538 11940

6705 21634 28150 43757 895 6547 20970 28914 30117 25736 41734 11392

22002 5739 27210 27828 34192 37992 10915 6998 3824 42130 4494 35739

8515 1191 13642 30950 25943 12673 16726 34261 31828 3340 8747 39225

18979 17058 43130 4246 4793 44030 19454 29511 47929 15174 24333 19354

16694 8381 29642 46516 32224 26344 9405 18292 12437 27316 35466 41992

15642 5871 46489 26723 23396 7257 8974 3156 37420 44823 35423 13541

42858 32008 41282 38773 26570 2702 27260 46974 1469 20887 27426 38553

22152 24261 8297

19347 9978 27802

34991 6354 33561

29782 30875 29523

9278 48512 14349

38061 4165 43878

8548 33172 34410

22535 28811 23950

20439 4027 24186

38618 8187 30947

35538 43880 21459

7091 45616 15063

5505 9315 21908

36046 32914 11836

7304 39782 33721

16905 29962 12980

11171 23709 22460

34541 9937 44500

14035 47316 8815

15057 45482 24461

30518 36877 879

7583 13364 24332

448 27056 4682

12083 31378 21670

1159 18031 2221

17028 38715 9350

17343 24530 29574

46128 31039 32818

20373 36967 18345

46685 20622 32806

Address of Parity Bit Accumulators (Rate ⅖)

5650 4143 8750 583 6720 8071 635 1767 1344 6922 738 6658

5696 1685 3207 415 7019 5023 5608 2605 857 6915 1770 8016

3992 771 2190 7258 8970 7792 1802 1866 6137 8841 886 1931

4108 3781 7577 6810 9322 8226 5396 5867 4428 8827 7766 2254

4247 888 4367 8821 9660 324 5864 4774 227 7889 6405 8963

9693 500 2520 2227 1811 9330 1928 5140 4030 4824 806 3134

1652 8171 1435

3366 6543 3745

9286 8509 4645

7397 5790 8972

6597 4422 1799

9276 4041 3847

8683 7378 4946

5348 1993 9186

6724 9015 5646

4502 4439 8474

5107 7342 9442

1387 8910 2660.

2. A method according to claim 1 , wherein the LDPC codes are represented by a coded signal that comprises an 8-bit cyclic redundancy check (CRC) code with generator polynomial (x 5 +x 4 +x 3 +x 2 +1)(x 2 x+1)(X+1).

3. A method according to claim 1 , further comprising:

accumulating information bits at parity bit addresses according to {x+m mod 360×q} mod(n ldpc −k ldpc ), where n ldpc is the codeword size, k ldpc is the information block size, m is an integer corresponding to a particular information bit, q is a code rate dependent constant, and x denotes the address of the parity bit accumulator as specified by the respective tables.

4. A method according to claim 3 , wherein the coded signal further comprises an outer code that is based on Bose Chaudhuri Hocquenghem (BCH) coding.

5. A method according to claim 3 , wherein, for the 1/3 rate code, q=120, n ldpc =64800, k ldpc =n BCH =21600, k BCH =21408 (12 bit error correcting BCH), n BCH being the codeword size for the BCH outer code, k BCH being the information block size for the BCH outer code.

6. A method according to claim 3 , wherein, for the 1/4 rate code, q=135, nu ldpc =64800, k ldpc =n BCH =16200, k BCH =16008 (12 bit error correcting BCH), n BCH being the codeword size for the BCH outer code, k BCH being the information block size for the BCH outer code.

7. A method according to claim 3 , wherein, for the 2/5 rate code, q=108, n ldpc =64800, k ldpc =n BCH =25920, k BCH =25728 (12 bit error correcting BCH), n BCH being the codeword size for the BCH outer code, k BCH being the information block size for the BCH outer code.

8. A method according to claim 1 , wherein the LDPC codes are represented by a coded signal, the method further comprising:

demodulating the LDPC coded signal according to one of 8-PSK (Phase Shift Keying), 16-QAM (Quadrature Amplitude Modulation), QPSK (Quadrature Phase Shift Keying), 16-APSK (Amplitude Phase Shift Keying) or 32-APSK.

9. A receiving device comprising:

a memory configured to store edge values used to compute parity check equations relating to Low Density Parity Check (LDPC) codes; and

a decoder configured to decode the LDPC codes based on the computed parity check equations, wherein the LDPC codes have one of a code rate of 1/3, a code rate of 1/4, or a code rate of 2/5 associated with respective tables each specifying addresses of parity bit accumulators,