Semiconductor integrated circuit device
The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.
1. A semiconductor integrated circuit device provided with an SRAM memory comprising:
an SRAM memory cell array including a plurality of SRAM memory cells arranged in a plurality of rows and a plurality of columns;
the SRAM memory cell including a first CMOS inverter, a second CMOS inverter, a first N-channel MOS transistor coupled to an output node of the first CMOS inverter, a second N-channel MOS transistor coupled to an output node of the second CMOS inverter, the first CMOS inverter including a first P-channel MOS transistor and the second CMOS inverter including a second P-channel MOS transistor;
a plurality of word lines coupled to the first and second N-channel MOS transistors corresponding to the SRAM memory cells of the rows;
a plurality of first bit lines coupled to the first N-channel MOS transistors corresponding to the SRAM memory cells of the columns, the first bit lines extended to a first side and a second side opposing the first side of the SRAM memory cell array;
a plurality of second bit lines coupled to the second N-channel MOS transistors corresponding to the SRAM memory cells of the columns, the second bit lines extended to the first side and the second side;
a power supply line that supplies a power voltage;
a plurality of power transistors coupled to the power supply line and the power transistors arranged corresponding to the SRAM memory cells of the columns;
a plurality of memory cell power supply lines coupled to corresponding ones of the power transistors and the memory cell power supply lines arranged along the first and second bit lines, and the memory cell power supply lines coupled to sources of the first and second P-channel MOS transistors in the SRAM memory cells corresponding to the columns;
a write driver that writes data to the SRAM memory cell;
a plurality of column selection switches coupled to corresponding ones of the first bit lines and the second bit lines, the column selection switches being arranged proximate the first side;
a signal line to control the power transistor; and
an output logic circuit to output a signal to the signal line,
wherein a first distance between the output logic circuit and the the column selection switch corresponding to a column of the memory cell array is shorter than a second distance between the output logic circuit and the memory cell in the column allocated at the second side of the memory cell array, and
wherein an on-resistance of the power transistor coupled to a write operation memory cell is higher than an on-resistance of the power transistor coupled to a read operation memory cell.
2. A semiconductor integrated circuit device according to claim 1 ,
wherein the SRAM memory cells have a first part, a second part and a third part, and the parts are arranged in order of the first part, the second part and the third part along the word line,
wherein the first part includes the first N-channel MOS transistor and a third N-channel MOS transistor of the first CMOS inverter,
wherein the second part includes the first P-channel MOS transistor of the first CMOS inverter and the second P-channel MOS transistor of the second CMOS inverter, and
wherein the third part includes the second N-channel MOS transistor and a fourth N-channel MOS transistor of the second CMOS inverter.
3. A semiconductor integrated circuit device according to claim 2 ,
wherein the first bit lines are arranged in the first parts of corresponding to the SRAM memory cells,
wherein the memory cell power supply lines are arranged in the second parts of corresponding to the SRAM memory cells, and
wherein the second bit lines are arranged in the third parts of corresponding to the SRAM memory cells.
4. A semiconductor integrated circuit device according to claim 3 , wherein the power transistor is a P-channel MOS transistor.
5. A semiconductor integrated circuit device provided with an SRAM memory comprising:
an SRAM memory cell array including a plurality of SRAM memory cells arranged in a plurality of rows and a plurality of columns;
the SRAM memory cell including a first CMOS inverter, a second CMOS inverter, a first N-channel MOS transistor coupled to an output node of the first CMOS inverter and a second N-channel MOS transistor coupled to an output node of the second CMOS inverter, the first CMOS inverter including a first P-channel MOS transistor and the second CMOS inverter including a second P-channel MOS transistor;
a plurality of word lines coupled to the first and second N-channel MOS transistors corresponding to the SRAM memory cells of the rows;
a plurality of first bit lines coupled to the first N-channel MOS transistors corresponding to the SRAM memory cells of the columns, the first bit lines extended to a first side and a second side opposing the first side of the SRAM memory cell array;
a plurality of second bit lines coupled to the second N-channel MOS transistors corresponding to the SRAM memory cells of the columns, the second bit lines extended to the first side and the second side;
a power supply line that supplies a power voltage;
a plurality of power transistors coupled to the power supply line and the power transistors arranged corresponding to the SRAM memory cells of the columns;
a plurality of memory cell power supply lines coupled to corresponding ones of the power transistors and the memory cell power supply lines arranged proximate the first and second bit lines, and the memory cell power supply lines coupled to sources of the first and second P-channel MOS transistors in the SRAM memory cells corresponding to the columns;
at least one write driver that writes data to the SRAM memory cells;
a sense amplifier transmitted a data from the first bit line and the second bit line, the sense amplifier being arranged the first side;
a signal line to control the power transistor; and
a logic circuit to output a signal from an output node to the signal line,
wherein a first distance between the output node of the logic circuit and the sense amplifier is shorter than a second distance between the output node of the logic circuit and the memory cell allocated at the second side of the memory cell array, and
wherein an on-resistance of the power transistor coupled to a memory cell for write operation is higher than an on-resistance of the power transistor coupled to a memory cell for read operation.
6. A semiconductor integrated circuit device according to claim 5 ,
wherein the SRAM memory cells have a first part, a second part and a third part, and the parts are arranged in order of the first part, the second part and the third part along the word line,
wherein the first part includes the first N-channel MOS transistor and a third N-channel MOS transistor of the first CMOS inverter,
wherein the second part includes the first P-channel MOS transistor of the first CMOS inverter and the second P-channel MOS transistor of the second CMOS inverter, and
wherein the third part includes the second N-channel MOS transistor and a fourth N-channel MOS transistor of the second CMOS inverter.
7. A semiconductor integrated circuit device according to claim 6 ,
wherein the first bit lines are arranged in the first parts of corresponding to the SRAM memory cells,
wherein the memory cell power supply lines are arranged in the second parts of corresponding to the SRAM memory cells, and
wherein the second bit lines are arranged in the third parts of corresponding to the SRAM memory cells.
8. A semiconductor integrated circuit device according to claim 7 , wherein the power transistor is a P-channel MOS transistor.
9. A semiconductor integrated circuit device provided with an SRAM memory comprising:
an SRAM memory cell array including a plurality of SRAM memory cells arranged in a plurality of rows and a plurality of columns;
the SRAM memory cell including a first CMOS inverter, a second CMOS inverter, a first N-channel MOS transistor coupled to an output node of the first CMOS inverter and a second N-channel MOS transistor coupled to an output node of the second CMOS inverter, the first CMOS inverter including a first P-channel MOS transistor and the second CMOS inverter including a second P-channel MOS transistor;
a plurality of word lines coupled to the first and second N-channel MOS transistors corresponding to the SRAM memory cells of the rows;
a plurality of first bit lines coupled to the first N-channel MOS transistors corresponding to the SRAM memory cells of the columns, the first bit lines extended to a first side and a second side opposing the first side of the SRAM memory cell array;
a plurality of second bit lines coupled to the second N-channel MOS transistors corresponding to the SRAM memory cells of the columns, the second bit lines extended to the first side and the second side;
a power supply line that supplies a power voltage;
a plurality of power transistors coupled to the power supply line and the power transistors arranged corresponding to the SRAM memory cells of the columns;
a plurality of memory cell power supply lines coupled to corresponding ones of the power transistors and the memory cell power supply lines arranged along the first and second bit lines;
a write driver that writes data to the SRAM memory cell, the write driver being arranged the first side;
a control signal line to control the power transistor; and
a control circuit coupled to the control signal line,
wherein a first distance between the control circuit and first edges of the first and second bit lines in a column of the first side is shorter than a second distance between the output node of the control circuit and second edges of the first and second bit lines in the column of the second side, and
wherein an on-resistance of the power transistor coupled to a write operation column is higher than an on-resistance of the power transistor coupled to a read operation column.
10. A semiconductor integrated circuit device according to claim 9 ,
wherein the SRAM memory cells have a first part, a second part and a third part, and the parts are arranged in order of the first part, the second part and the third part along the word line,
wherein the first part includes the first N-channel MOS transistor and a third N-channel MOS transistor of the first CMOS inverter,
wherein the second part includes the first P-channel MOS transistor of the first CMOS inverter and the second P-channel MOS transistor of the second CMOS inverter, and
wherein the third part includes the second N-channel MOS transistor and a fourth N-channel MOS transistor of the second CMOS inverter.
11. A semiconductor integrated circuit device according to claim 10 ,
wherein the first bit lines are arranged in the first parts of corresponding to the SRAM memory cells,
wherein the memory cell power supply lines are arranged in the second parts of corresponding to the SRAM memory cells, and
wherein the second bit lines are arranged in the third parts of corresponding to the SRAM memory cells.
12. A semiconductor integrated circuit device according to claim 11 ,
wherein the power transistor is a P-channel MOS transistor.