Recursive range controller

1. A method for detecting out-of-specification data streams by a controller circuit comprising:

receiving data over a plurality of evaluation periods;

segmenting each evaluation period into n sub-periods, each of the n sub-periods having a same length, each of the n sub-periods spanning a portion of the data, wherein n is a positive integer;

evaluating corresponding data starting at an end of each n sub-periods to determine whether the corresponding data are the out-of-specification data, wherein the evaluating the corresponding data starts at an end of an n-th sub-period of a first evaluation period and finishes at an end of a corresponding n-th sub-period of a second evaluation period that follows the first evaluation period.

2. The method of claim 1 , wherein evaluating further comprises:

evaluating the corresponding data starting at the end of each of an n-th subperiod for a length substantially equal to each evaluation period.

3. The method of claim 1 , wherein each evaluation period has the same length.

4. The method of claim 1 , wherein evaluating comprises, at the end of each of the n sub-periods:

capturing a value of a counter;

processing the captured value; and

synchronously setting the counter value to zero.

5. The method of claim 4 , wherein processing comprises:

saving the captured count value into a first register;

saving an n-th previous captured count;

using a first logic circuit to sum the captured count with a result from a previous count sum and generate a summed result;

using a second logic circuit to subtract the n-th previous captured count from the summed result to generate a subtraction result; and

checking if the subtraction result is within a predetermined operating range.

6. The method of claim 5 , wherein the subtraction result is substantially equivalent to the count of one evaluation period.

7. An apparatus for detecting out-of-specification data streams, comprising:

a receiver configured to receive data over a plurality of evaluation periods;

a divider coupled to the receiver, the divider configured to segment each evaluation period into n sub-periods, each having a same length, each of the n sub-periods spanning a portion of the data, wherein n is a positive integer; and

an evaluator coupled to the divider, wherein the evaluator is configured to evaluate corresponding data starting at an end of each of the n sub-periods, and the evaluation of the corresponding data starts at an end of an n-th sub-period of a first evaluation period and finishes at an end of a corresponding n-th sub-period of a second evaluation period that follows the first evaluation period.

8. The apparatus of claim 7 , wherein the evaluator is configured to evaluate the corresponding data period starting at each of the n sub-periods for a length substantially equal to each evaluation period.

9. The apparatus of claim 7 , wherein each evaluation period has the same length.

10. The apparatus of claim 7 , wherein the divider further comprises:

a first to capture a count;

a memory storage element coupled to store an n-th previous captured count;

a first logic circuit having a first input coupled to the first register to receive the count the first logic circuit having a second input to receive a subtraction result, the first logic circuit to sum the count with the subtraction result and generate a summed result;

a second logic circuit coupled to the first logic circuit to receive the summed result, the second logic circuit coupled to the memory storage element to receive the n-th previous captured count, the second logic circuit to subtract the summed result from the n-th previous captured count and generate the subtraction result; and

a result register coupled to the second logic circuit to receive the subtraction result.

11. The apparatus of claim 10 , wherein the evaluator further comprises:

a comparator coupled to the result register to compare the subtraction result with an input comparand, the input comparand indicating a predetermined operating range of the apparatus.

12. The apparatus of claim 10 , wherein the memory storage element is a first-in-firstout (FIFO) register.

13. The apparatus of claim 10 , wherein each of the first and second logic circuits are arithmetic logic units.

14. The apparatus of claim 10 , wherein each of the first and second logic circuits includes a Gray-code counter.

15. The apparatus of claim 10 , wherein the first logic circuit is different than the second logic circuit.

16. The apparatus of claim 10 further comprising:

a first counter receiving a first clock signal;

a second counter receiving a second clock signal, the second counter coupled to the first register;

a sub-period trigger circuit coupled to the first counter; and

a control state machine circuit coupled to the sub-period trigger circuit, the control state machine circuit to receive the second clock signal, and to synchronously reset the sub-period trigger circuit and the second counter, and capture the counter state in the first register.

17. The apparatus of claim 16 , wherein the first clock signal includes a local reference clock signal, and the second clock signal includes a recovered clock signal.

18. An apparatus for detecting out-of-specification data streams, comprising:

a receiver configured to receive data over a plurality of evaluation periods;

means for segmenting each evaluation period into n sub-periods, each having a same length, each of the n sub-periods spanning a portion of the data, wherein n is a positive integer;

means for evaluating corresponding data starting at an end of each of the n sub-periods, wherein the evaluating the corresponding data starts at an end of an n-th sub-period of a first evaluation period and finishes at an end of a corresponding n-th sub-period of a second evaluation period that follows the first evaluation period.