Method and apparatus for testing delay faults
An apparatus or method for testing of a SOC processor device may minimize interference that is caused by interfacing a comparatively low-speed testing device with the high-speed processor during testing. Implementations may gate the input clock signal at the clock input to each domain of the SOC processor device rather than at the output of the PLL clock. The gating of the clock signal to each domain may then be controlled by clock stop signals generated by the testing device and sent to the individual domains of the processor device. Gating the clock signal at the domain may provide a more natural state for the circuit during testing as well as allow the test control unit to test the different domains of the SOC device individually.
1. A method for testing at least one domain of a processor device including a plurality of domains, the method comprising:
generating at least a first clock stop signal and a second clock stop signal at a clock control module;
transmitting the first clock stop signal to a first gate coupled to a first one of the plurality of domains;
transmitting the second clock stop signal to a second gate coupled to a second one of the plurality of domains; and
serially controlling propagation of a clock signal into:
the first domain at the first gate by deasserting the first clock stop signal during a first time period; and
the second domain at the second gate by deasserting the second clock stop signal during a second time period;
wherein the second period of time occurs after the first period of time; and
wherein the first gate only controls propagation of the clock signal into the first domain, and wherein the second gate only controls propagation of the clock signal into the second domain; and
serially testing the first domain and second domain by:
providing a test pattern to the first domain while deasserting the first clock stop signal at the first gate; and
providing a new test pattern to the second domain while deasserting the second clock stop signal at the second gate.
2. The method of claim 1 wherein the controlling propagation further comprises:
deasserting the first clock stop signal to open the first gate and allow the clock signal to propagate into the first domain;
maintaining the open first gate for a desired number of clock pulses; and
asserting the first clock stop signal to close the first gate and prevent the clock signal from propagating into the first domain.
3. The method of claim 1 further comprising:
loading a first value into a counter, the first value indicative of a desired number of clock pulses.
4. The method of claim 3 wherein the controlling propagation further comprises:
deasserting the first clock stop signal to open the first gate;
decrementing the counter from the first value upon opening the first gate; and
asserting the first clock stop signal to close the first gate when the counter reaches zero.
5. The method of claim 4 wherein the decrementing operation further comprises: decrementing the counter at a same frequency as the clock signal.
6. The method of claim 4 further comprising:
loading a second value into the counter after the first gate is closed;
decrementing the counter from the second value upon opening the second gate; and
closing the second gate when the counter reaches zero.
7. The method of claim 1 wherein controlling the propagation comprises:
controlling a plurality of gates, the plurality of gates each coupled to a respective domain of the plurality of domains of the processor device, wherein the plurality of gates are configured to serially control propagation of a clock signal into the respective domains of the processor device.
8. The method of claim 7 wherein controlling the propagation further comprises:
transmitting a plurality of clock stop signals to the plurality of gates to close the plurality of gates;
deasserting at least one of the plurality of clock stop signals to open at least one gate of the plurality of gates while maintaining remaining gates closed;
maintaining the at least one gate open for a desired number of clock pulses; and
asserting at least one of the plurality of clock stop signals to close the at least one gate upon occurrence of the desired number of clock pulses with the at least one gate open.
9. The method of claim 1 further comprising:
providing the test pattern to the processor device; and
providing a scan enable signal to the processor device, wherein, upon receipt of the scan enable signal, the processor scans in the test pattern.
10. A system for testing at least one domain of a processor device including a plurality of domains, the system comprising:
a first gate coupled to a first domain to propagate a clock signal into the first domain;
a second gate coupled to a second domain to propagate the clock signal into the second domain;
a clock gate controller to:
generate at least:
a first clock stop signal to control propagating of the clock signal into the first domain at the first gate; and
a second clock stop signal to control propagating of the clock signal into the second domain at the second gate; and
dessert the first clock stop signal during a first time period to propagate the clock signal into the first domain; and
dessert the second clock stop signal during a second time period to propagate the clock signal into the second domain, wherein the second time period occurs after the first time period; and
serially test the first domain and second domain by:
providing a test pattern to the first domain while deasserting the first clock stop signal; and
providing a new test pattern to the second domain while deasserting the second clock stop signal.
11. The system of claim 10 further comprising:
a pattern generator configured to provide the test pattern to the processor device; and a counter operably connected to the clock gate controller.
12. The system of claim 11 wherein the counter decrements from a provided value, the provided value indicative of a desired number of clock pulses.
13. The system of claim 12 wherein the clock gate controller closes the first gate coupled to the first domain when the counter reaches zero.
14. The system of claim 10 wherein the clock gate controller is configured to control a plurality of gates, the plurality of gates each coupled to a respective domain of the plurality of domains of the processor device.
15. A computer-implemented system for testing at least one domain of a processor device including a plurality of domains, the system comprising:
a first gate coupled to a first domain to propagate a clock signal into the first domain;
a second gate coupled to a second domain to propagate the clock signal into the second domain;
a clock gate controller to:
generate at least:
a first clock stop signal to control propagating of the clock signal into the first domain at the first gate; and
a second clock stop signal to control propagating of the clock signal into the second domain at the second gate; and
dessert the first clock stop signal during a first time period to propagate the clock signal into the first domain; and
dessert the second clock stop signal during a second time period to propagate the clock signal into the second domain, wherein the second time period occurs after the first time period; and
serially test the first domain and second domain by:
providing a test pattern to the first domain while deasserting the first clock stop signal; and
providing a new test pattern to the second domain while deasserting the second clock stop signal.
16. The system of claim 15 further comprising:
a pattern generator module configured to provide the test pattern to the processor device; and
a counter module operably connected to the clock gate controller module.
17. The system of claim 16 wherein the counter module decrements from a provided value, the value provided indicative of a desired number of clock pulses.
18. The system of claim 17 wherein the clock gate controller module closes the first gate coupled to the first domain when the counter reaches zero.
19. The system of claim 15 wherein the clock gate controller module is configured to control a plurality of gates, the plurality of gates each coupled to a respective domain of the plurality of domains of the processor device.