Search engine for a receive equalizer
A search engine selects initial coefficients for a receive equalizer. The search engine may be incorporated into a communication receiver that includes a decision feedback equalizer and clock and data recovery circuit. Here, the search engine may initialize various adaptation loops that may control the operation of, for example, a decision feedback equalizer, a clock and data recovery circuit and a continuous time filter. The receiver may include an analog-to-digital converter that is used to generate soft decision data for some of the adaptation loops.
1. A method of identifying a coefficient for a receive equalizer comprising:
identifying which coefficient combinations from a first group or, if none in the first group, a second group of sets of coefficients that enable a clock recovery circuit to lock to a received signal;
calculating an error value associated with a received signal when the at least one equalizer component is configured with each of the identified sets of coefficients; and
selecting, based on the error value calculation, one of the identified sets of coefficients.
2. The method of claim 1 wherein: the at least one equalizer component comprises a plurality of equalizer components; each of the sets of coefficients comprises a plurality of coefficients; and determining comprises sequentially configuring the equalizer components with each set of coefficients.
3. The method of claim 1 comprising defining a plurality of groups of the sets of coefficients, wherein the determining comprises initially determining whether the clock recovery circuit locks when the at least one equalizer component is configured with sets of coefficients from a first one of the groups.
4. The method of claim 1 wherein calculating comprises calculating a mean square error associated with a received signal when the at least one equalizer component is configured with a set of coefficients from the second group.
5. The method of claim 1 comprising enabling optimization of a clock loop for an analog to digital converter in the receiver before calculating the mean square error.
6. The method of claim 1 wherein an analog to digital converter samples the received signal to provide data for the error value calculation.
7. The method of claim 6 comprising enabling optimization of a clock loop for the analog to digital converter before calculating the mean square error.
8. The method of claim 7 wherein the optimizing is associated with aligning a clock for the analog to digital converter with a clock for a retimer that retimes the received signal.
9. The method of claim 1 wherein selecting comprising selecting a set of coefficients associated with a lowest mean square error.
10. The method of claim 1 wherein determining comprises sequentially configuring the at least one equalizer component with each of the sets of coefficients.
11. The method of claim 1 wherein the coefficients in each set are predefined.
12. The method of claim 1 wherein the at least one equalizer component comprises at least one of a continuous time filter, a phase adjust circuit for the clock recovery circuit and a decision feedback equalizer.
13. The method of claim 1 wherein the identifying, calculating and selecting are performed when the receiver is initialized.
14. The method of claim 1 wherein the identifying, calculating and selecting are performed before invoking a tracking mode.
15. A communications system comprising:
a filter for filtering a received signal in accordance with at least one coefficient generated by a first adaptation loop;
an equalizer adapted to reduce channel related distortion in the received signal in accordance with at least one equalizer coefficient generated by a second adaptation loop;
a clock recovery circuit adapted to recover a clock signal from the received signal; and
a search engine configured to select an initial set of coefficients for at least one of the adaptation loops from at least a first and a second group of sets of coefficients, the search engine configured to:
identify which sets of combinations from a first group or, if none in the first group, a second group of sets of coefficients that enable the clock recovery circuit to lock;
obtain an error value derived from the received signal when the at least one of the adaptation loops is configured with each of the identified sets of coefficients; and
select, based on the error value calculation, one of the identified sets of coefficients as the initial set of coefficients.
16. The system of claim 15 comprising: an analog to digital converter, clocked by a sampling clock signal, to generate data for the adaptation loops; and a mean square error component configured to calculate the mean square error in accordance with the data.
17. The system of claim 16 comprising: a delay lock loop for generating the sampling clock; and a relative error adaptation loop adapted to adjust a phase of the sampling clock in accordance with a comparison of data from two different data paths.
18. The system of claim 16 comprising a phase adjust circuit for adjusting a phase of the clock signal in accordance with at least one phase adjust coefficient generated by a third adaptation loop.
19. The system of claim 15 comprising a clock loop for an analog to digital converter wherein the clock loop is allowed to optimize before the error value is obtained.
20. An apparatus comprising:
means for identifying coefficient combinations from a first one of a plurality of groups that enable a clock recovery circuit to lock to a received signal;
means for, if the clock recovery circuit does not acquire lock for any of the coefficient combinations from the first set, identifying coefficient combinations from a subsequent one of the groups that enable the clock recovery circuit to lock to the received signal;
means for calculating an error value associated with the received signal when the equalizer components are configured with each of the identified coefficient combinations; and
means for selecting, based on the error value calculation, one of the identified coefficient combinations.
21. The apparatus of claim 20 wherein the first group includes a smaller number of coefficient combinations than the subsequent group.
22. The apparatus of claim 20 comprising means for enabling an optimization of a clock loop for an analog to digital converter in the receiver prior to calculating the mean square error.