Nonvolatile semiconductor memory device including pillars buried inside through holes
In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.
1. A nonvolatile semiconductor memory device comprising:
a substrate;
a semiconductor region formed in an upper portion of the substrate;
a plurality of dielectric films and electrode films which are alternately stacked on the substrate;
conductor pillars connected to the semiconductor region and not connected to the electrode films, the conductor pillars penetrating the plurality of the dielectric films and the electrode films;
semiconductor pillars penetrating the plurality of the dielectric films and the electrode films, and connected to the semiconductor region;
a shunt interconnect provided above the plurality of dielectric films and electrode films and connected to the conductor pillars;
a bit interconnect provided above the plurality of dielectric films and electrode films and connected to the semiconductor pillars; and
a charge storage layer provided at least between the semiconductor pillar and some of the electrode films,
the conductor pillar having a lower resistivity than the semiconductor pillar.
2. The memory device according to claim 1 , wherein the conductor pillar is formed from a metal, and the semiconductor pillar is formed from a semiconductor doped with impurities.
3. The memory device according to claim 1 , wherein
the conductor pillars are located at a center portion of the matrix composed of the conductor pillars and the semiconductor pillars.
4. The memory device according to claim 1 , wherein the shunt interconnect and the bit interconnect are located at an equal height.
5. The memory device according to claim 1 , wherein the shunt interconnect and the bit interconnect are each formed from a metal.
6. The memory device according to claim 1 , wherein the shunt interconnect is provided immediately above the conductor pillars and connected to an upper end portion of the conductor pillars.
7. The memory device according to claim 1 , wherein
a plurality of stacked bodies each with a plurality of the dielectric films and the electrode films alternately stacked are provided along a same direction, and
the shunt interconnect is continuously disposed so as to extend immediately above the plurality of stacked bodies.