Integrated ramp, sweep fractional frequency synthesizer on an integrated circuit chip

1. An integrated ramp, sweep fractional frequency synthesizer system with a fractional divider, the synthesizer system comprising:

an integrated circuit chip including a plurality of elements of a fractional frequency synthesizer including a modulator for modifying the divisor of said fractional divider; a ramp generator on the same integrated circuit chip; said ramp generator being responsive to a trigger signal to generate a ramp for sweeping the frequency of said fractional frequency synthesizer; and an interface circuit responsive to an external controller, to control the ramp generator and modulator.

2. The integrated ramp, sweep fractional frequency synthesizer of claim 1 in which said fractional divider is on said integrated circuit chip.

3. The integrated ramp, sweep fractional frequency synthesizer of claim 1 in which said ramp generator includes a look-up table containing a number of different shaped ramps.

4. The integrated ramp, sweep fractional frequency synthesizer of claim 1 in which said ramp generator includes a ramp controller containing a programmed number of ramp steps and step sizes and being responsive to a trigger signal to generate a ramp shape.

5. The integrated ramp, sweep fractional frequency synthesizer of claim 1 in which said ramp generator includes a calculator circuit for calculating one or more different ramp shapes.

6. The integrated ramp, sweep fractional frequency synthesizer of claim 1 in which said calculator circuit calculates exponential or parabolic ramp shapes.

7. The integrated ramp, sweep fractional frequency synthesizer system of claim 4 in which said ramp controller includes a single mode for generating a ramp upon each trigger signal.

8. The integrated ramp, sweep fractional frequency synthesizer system of claim 4 in which said ramp controller includes an automatic mode for enabling repeated ramping upon a single trigger signal and is further programmed with a dwell time to define a repetition period.

9. The integrated ramp, sweep fractional frequency synthesizer system of claim 1 in which said fractional frequency synthesizer also has integrated on the chip the fractional divider for dividing a voltage controlled oscillator (VCO) feedback path, a loop filter, a charge pump for driving said loop filter and a phase frequency detector, for detecting any deviation between a reference and VCO, a VCO driven by said loop filter to develop a compensation signal to enable the loop filter to converge the VCO output with the reference, a fixed divider to condition the VCO signal, and a reference path divider.

10. The integrated ramp, sweep fractional frequency synthesizer system of claim 4 wherein said interface includes a serial or parallel interface circuit on said integrated circuit chip for receiving off-chip commands to program said ramp controller.

11. The integrated ramp, sweep fractional frequency synthesizer system of claim 4 in which said modulator includes a modulator core responsive to a fractional portion of said ramp controller output and an integer delay path circuit responsive to an integer portion of said ramp controller output to synchronize an integer and a fractional outputs from said modulator to said fractional divider.

12. The integrated ramp, sweep fractional frequency synthesizer system of claim 11 in which said integer delay path circuit includes a delay circuit responsive to the integer portion of said ramp controller output and a summing circuit for combining the delayed integer portion and the fractional output of said modulator core.

13. The integrated ramp, sweep fractional frequency synthesizer system of claim 1 in which said ramp is a simple ramp extending in a single direction.

14. The integrated ramp, sweep fractional frequency synthesizer system of claim 1 in which said ramp is a compound ramp extending in a number of directions.

15. The integrated ramp, sweep fractional frequency synthesizer system of claim 1 in which said ramp is a compound ramp extending in at least a first direction and a second generally opposite direction.

16. The integrated ramp, sweep fractional frequency synthesizer system of claim 1 in which said trigger signal is hardware generated from an input pin.

17. The integrated ramp, sweep fractional frequency synthesizer system of claim 1 in which said trigger signal is software generated from a serial/parallel interface (SPI).

18. The integrated ramp, sweep fractional frequency synthesizer system of claim 1 in which said trigger signal is an auto-mode sweep trigger signal.

19. The integrated ramp, sweep fractional frequency synthesizer system of claim 1 in which said trigger signal is a bi-directional mode sweep trigger signal.

20. The integrated ramp, sweep fractional frequency synthesizer system of claim 1 in which said ramp generator has a single step mode where each trigger advances said sweep by one step per trigger.

21. The integrated ramp, sweep fractional frequency synthesizer of claim 1 in which the modulator is of ΔΣ type.

22. A fractional frequency synthesizer system with a frequency sweeper integrated on a chip including an integrated modulator, an integrated ramp generator for generating a ramp to sweep the frequency of said fractional frequency synthesizer and an integrated serial/parallel interface (SPI) or parallel interface on the same chip, where any of other synthesizer components selected from any of a fractional divider, a charge pump, a phase detector, a loop filter, and a voltage controlled oscillator (VCO) are located on or off the chip.