Precharge circuits and methods for content addressable memory (CAM) and related devices
A method may include selectively coupling a result line to a reference node in response to a compare data value being applied to a plurality of compare cell circuits; precharging the result line to the precharge potential by enabling a first precharge path while the compare data value is being applied; and after precharging the result line by enabling the first precharge path, disabling the first precharge path to place it in a high impedance state.
1. A method, comprising:
selectively coupling a result line to a reference node in response to a compare data value being applied to a plurality of compare cell circuits;
precharging the result line to a precharge potential by enabling a first precharge path while the compare data value is being applied;
after precharging the result line by enabling the first precharge path, disabling the first precharge path to place it in a high impedance state; and
disabling the first and second precharqe paths in response to at least validity data that indicates validity of data stored in the compare cell circuits.
2. The method of claim 1 , wherein:
precharging the result line by enabling the first precharge path includes enabling the first precharge path in response to at least a periodic clock signal.
3. The method of claim 1 , wherein:
disabling the first precharge path includes disabling the first precharge path in response to at least a periodic clock signal.
4. The method of claim 3 , wherein:
disabling the first precharge path includes disabling the first precharge path further in response to at least a potential of the result line.
5. The method of claim 1 , wherein:
the compare data value is applied to the compare cell circuits in response to a periodic signal.
6. The method of claim 1 , further including:
precharging the result line to the precharge potential by enabling and disabling the second precharge path before the compare data value is applied.
7. An integrated circuit device, comprising:
a compare cell circuit that couples a result line to a reference voltage according to a comparison result between a stored data value and an applied compare data value during a compare time period; and
a first precharge circuit that is enabled to provide a low impedance path between the result line and a precharge voltage node during a portion of a precharge period preceding the compare time period, and is disabled to substantially isolate the result line from the precharge voltage node during a portion of the compare time period.
8. The integrated circuit device of claim 7 , wherein:
the first precharge circuit is disabled in response to at least a periodic signal.
9. The integrated circuit device of claim 8 , further including:
a plurality of compare data lines coupled to the compare cell circuit that provide the applied compare data value in response to the periodic signal.
10. The integrated circuit device of claim 7 , wherein:
the first precharge circuit is disabled in response to at least a potential of the result line.
11. The integrated circuit device of claim 7 , further including:
a second precharge circuit that is enabled to provide a low impedance path between the result line and the precharge voltage node during a portion of the precharge period, and is disabled to substantially isolate the result line from the precharge voltage node prior to the compare time period.
12. The integrated circuit device of claim 11 , wherein:
the second precharge circuit is enabled in response to at least a periodic clock signal.
13. The integrated circuit device of claim 7 , wherein:
the compare cell circuit includes a plurality of content addressable memory (CAM) cells having at least two transistors of a first conductivity type arranged in series with one another; and
the first precharge circuit includes at least one transistor of a second conductivity type.
14. An integrated circuit device, comprising:
a compare cell circuit that selectively couples a result line to a reference voltage according to a comparison result between a stored data value and an applied compare data value during a compare period;
a first precharge path to the result line that is enabled during a portion of a precharge period which precedes the compare time period, and disabled during the compare time period; and
a second precharge path to the result line that is enabled during at least a portion of the precharge period, and disabled during at least a portion of the compare period; wherein
the first and second precharge paths are disabled in response to at least validity data that indicates a validity of the data stored value in the compare cell circuit.
15. The integrated circuit device of claim 14 , wherein:
the first precharge path is enabled in the precharge period prior to the second precharge path being enabled in the precharge period.
16. The integrated circuit device of claim 14 , wherein:
the first precharge path is disabled in the precharge period prior to the second precharge path being enabled in the precharge period.
17. The integrated circuit device of claim 14 , wherein:
the first precharge path is disabled in the precharge period after the second precharge path is enabled in the precharge period.
18. The integrated circuit of claim 14 , further including:
a precharge control circuit coupled to receive at least one periodic clock signal that generates a first control signal and a second control signal; and
the first precharge path is enabled and disabled in response to at least the first control signal; wherein
the second precharge path is enabled and disabled in response to at least the second control signal.