IP Library Granted Patent US 8,093,592
Granted Patent B2
US 8,093,592 · App. 12/748,452 · Granted Jan 10, 2012

Thin film transistor substrate, electronic apparatus, and methods for fabricating the same

Assignee: Au Optronics Corporation
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Quick Facts
Patent No.
US 8,093,592
App. No.
12/748,452
Granted
Jan 10, 2012
Kind
B2
Abstract

A TFT substrate includes a substrate and at least a TFT disposed thereon. The TFT includes a semiconductor island and at least a gate. The semiconductor island has a source region, a drain region, and a channel region interposed therebetween. The semiconductor island has sub-grain boundaries. The gate corresponds to the channel region. A first included angle between an extending direction of the gate and a line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 90 degrees. A second included angle between the sub-grain boundaries in the channel region and the line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 0 degree or 90 degrees. Additionally, a method of fabricating a TFT substrate, an electronic apparatus, and a method of fabricating the electronic apparatus are also provided.

Claims (18)

1. A thin film transistor substrate, comprising:

a substrate;

at least a thin film transistor, disposed on the substrate and comprising:

a semiconductor island, comprising a plurality of sub-grain boundaries, a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein a length of the channel region projected in the substrate is extended along a curve, and the width of the channel region projected in the substrate remains substantially the same in an extending direction of the curve; and

a gate, corresponding to the channel region.

2. The thin film transistor substrate of claim 1 , wherein the length of the channel region is substantially equal to the total length of the curve in the channel region.

3. The thin film transistor substrate of claim 1 , wherein the curve has an inflection point.

4. The thin film transistor substrate of claim 1 , wherein the curve comprises two curved ends and a straight portion, the straight portion is connected between the two curved ends, and the two curved ends are adjacent to the source region and the drain region, respectively.

5. The thin film transistor substrate of claim 4 , wherein the two curved ends are bent in different directions with reference to the straight portion serving as a baseline.

6. The thin film transistor substrate of claim 4 , wherein in the channel region extended along the straight portion, the sub-grain boundaries are substantially parallel to an extending direction of the straight portion.

7. The thin film transistor substrate of claim 4 , wherein the two curved ends are bent in the same direction with reference to the straight portion serving as a baseline.

8. A method for fabricating a thin film transistor substrate, the method comprising:

providing a substrate;

forming at least a semiconductor island on the substrate, the semiconductor island comprising a plurality of sub-grain boundaries;

respectively defining a source region, a drain region, and a channel region located between the source region and the drain region in the semiconductor island, wherein the length of the channel region is extended along a curve, and the width of the channel region remains substantially the same in an extending direction of the curve; and

forming at least a gate corresponding to the channel region.

9. An electronic apparatus comprising a display panel and an electronic component connected to the display panel, wherein the display panel comprises the thin film transistor substrate of claim 1 .

10. A method for fabricating an electronic apparatus, the method comprising providing a display panel and an electronic component connected to the display panel, wherein a method for fabricating the display panel comprises a method for fabricating the thin film transistor substrate of claim 8 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 24, 2025
From: AUO CORPORATION
To: NEOLAYER LLC
Reel/Frame 072266/0941 →
Priority Claims (1)
TW 97128473 A · Jul 25, 2008 · national
Continuity (2)
Division 12249968 · Oct 13, 2008
Related Publication 20100176402A1 · Jul 15, 2010