Power amplifier
There is provided a power amplifier that can maintain a constant gain by detecting a level of a signal being input and a level of a signal being output. A power amplifier according to an aspect of the invention may include: an amplification section having at least one amplification unit amplifying an input signal according to an adjustable gain to thereby output the amplified input signal; a detection section detecting signal levels of an input signal and an output signal of the amplification section; and a gain maintaining section controlling a bias power according to a detection result of the detection section so that a gain of the amplification section is maintained within a predetermined gain range.
1. A power amplifier comprising:
an amplification section amplifying an input signal according to an adjustable gain to thereby output the amplified input signal;
a detection section detecting signal levels of an input signal and an output signal of the amplification section; and
a gain maintaining section controlling a bias power according to a detection result of the detection section so that a gain of the amplification section is maintained within a predetermined gain range,
wherein the gain maintaining section comprises:
a gain calculations unit calculating the gain of the amplification section according to the detection result of the detection section;
a comparison unit performing a comparison to determine whether a calculation results of the gain calculation unit is within the predetermined gain range; and
a bias supply unit supplying a corresponding bias power according to a result of the comparison of the comparison unit,
wherein the comparison unit comprises:
a first comparator having a positive (+) terminal receiving the calculation result of the gain calculation unit and a negative (−) terminal receiving a first-range voltage having a predetermined voltage level; and
a second comparator having a negative (−) terminal receiving the calculation result of the gain calculation unit and a positive (+) terminal receiving a second-range voltage having a predetermined voltage level lower than the predetermined voltage level of the first-range voltage.
2. The power amplifier of claim 1 , wherein the detection section comprises:
an input peak detector detecting the signal level of the input signal; and
an output peak detector detecting the signal level of the output signal.
3. The power amplifier of claim 1 , wherein the bias supply unit comprises:
a bit setting unit determining whether to increase, reduce, or maintain a bit value according to a comparison result of the comparison section;
a control unit supplying a digital signal corresponding to a predetermined bias voltage according to a bit of the bit setting unit; and
a bias voltage supply unit supplying a bias voltage corresponding to the digital signal of the control unit.
4. The power amplifier of claim 3 , wherein the control unit comprises:
a logic gate performing a logical operation on the bit of the bit setting unit;
a first multiplexer selecting a high-level signal or a low-level signal according to the bit of the bit setting unit;
a first flip-flop performing a D flip-flop operation on an addition result according to input data;
a first adder adding a selection value of the first multiplexer and a value of the D flip-flop operation of the first flip-flop and transmitting an addition result to the first flip-flop;
a second multiplexer selecting a high-level signal or a low-level signal according to a result of the logical operation from the logic gate;
a second flip-flop performing a D flip-flop operation on an addition result according to input data;
a second adder adding a selection value of the second multiplexer and a value of the D flip-flop operation of the second flip-flop and transmitting an addition result to the second flip-flop;
a third multiplexer selecting a high-level signal or a low-level signal according to the logical operation result from the logic gate;
a third flip-flop performing a D flip-flop operation on an addition result according to input data; and
a third adder performing a selection value of the third multiplexer and a value of the D flip-flop operation of the third flip-flop and transmitting an addition result to the third flip-flop.
5. The power amplifier of claim 1 , further comprising an input impedance matching section matching an impedance of a path through which the input signal, being input to the amplification section, is transmitted.
6. The power amplifier of claim 1 , further comprising an output impedance matching section matching an impedance of a path through which the output signal, being output from the amplification section, is transmitted.