Fast SERDES I/O characterization
A system and method to perform automatic testing of a device using Design-for-Test functionality built-in a pair of serializer/deserializer (SERDES) of the device to perform I/O characterization with respect to clock jitter in a self-test mode. Performance of a SERDES operating with jitter injected clock signal is characterized by forming a self-test loop-back configuration with another SERDES operating with a clean clock signal where the clean clock signal and the jitter injected clock signal are supplied by a simplified tester.
1. A tester for characterizing a device under test (DUT) comprising first and second serializer/deserializer (SERDES) modules, comprising:
a first conductor adapted to, when the DUT is operatively coupled to the tester, couple a transmit (TX) output of the first SERDES module to a receive (RX) input of the second SERDES module;
a first clock generator configured to, when the DUT is operatively coupled to the tester, clock the first SERDES module using a first clock signal;
a second clock generator configured to, when the DUT is operatively coupled to the tester, clock the second SERDES module using a second clock signal, wherein the first clock signal is equivalent to the second clock signal with a first jitter; and
a functional module configured to, when the DUT is operatively coupled to the tester, receive a first test result from the DUT by configuring the DUT to:
convert, using the first SERDES module based on the first clock, first parallel test data generated by a first test pattern generator comprised in the DUT into first serial test data at the TX output of the first SERDES module, wherein the first serial test data is communicated to the RX input of the second SERDES module via the first conductor;
convert, using the second SERDES module based on the second clock, the first serial test data at the RX input of the second SERDES module into first parallel verification data; and
generate the first test result by analyzing the first parallel verification data based on a first pre-determined criterion using a first test pattern verifier comprised in the DUT.
2. The tester of claim 1 ,
wherein analyzing the first parallel verification data based on a first pre-determined criterion is by comparing the first parallel verification data to a delayed version of the first parallel test data,
wherein the first test result comprises a first bit error rate, and
wherein the functional module is further configured to:
adjust the first jitter;
receive an adjustment of the first test result from the DUT responsive to adjusting the first jitter; and
generate a characterization result of the first SERDES module based at least on the first test result and the adjustment of the first test result.
3. The tester of claim 1 , the DUT further comprising third and fourth SERDES modules, the tester further comprising:
a second conductor adapted to, when the DUT is operatively coupled to the tester, couple a transmit (TX) output of the third SERDES module to a receive (RX) input of the fourth SERDES module;
wherein the functional module is further configured to, when the DUT is operatively coupled to the tester, receive a second test result concurrently with receiving the first test result, from the DUT,
wherein the DUT is further configured by the functional module to:
convert, using the third SERDES module, second parallel test data generated by a second test pattern generator comprised in the DUT into second serial test data at the TX output of the third SERDES module, wherein the second serial test data is communicated to the RX input of the fourth SERDES module via the second conductor;
convert, using the fourth SERDES module, the second serial test data at the RX input of the fourth SERDES module into second parallel verification data; and
generate the second test result, concurrently with generating the first test result, by analyzing the second parallel verification data based on a second pre-determined criterion using a second test pattern verifier comprised in the DUT.
4. The tester of claim 3 ,
wherein the first clock generator is further configured to, when the DUT is operatively coupled to the tester, clock the third SERDES module using the first clock signal,
wherein the second clock generator is further configured to, when the DUT is operatively coupled to the tester, clock the fourth SERDES module using the second clock signal,
wherein the DUT converting the second parallel test data into the second serial test data is based on the first clock, and
wherein the DUT converting the second serial test data into the second parallel verification data is based on the second clock.
5. The tester of claim 4 , wherein the functional module is further configured to:
adjust the first jitter;
receive an adjustment of the first and second test results responsive to adjusting the first jitter; and
generate a characterization result of the first and second SERDES modules concurrently based at least on the first and second test results and the adjustment of the first and second test results.
6. The tester of claim 3 , the DUT further comprising third and fourth SERDES modules, the tester further comprising:
a third clock generator configured to, when the DUT is operatively coupled to the tester, clock the third SERDES module using a third clock signal; and
a fourth clock generator configured to, when the DUT is operatively coupled to the tester, clock the fourth SERDES module using a fourth clock signal, wherein the third clock signal is equivalent to the fourth clock signal with a second jitter,
wherein the DUT converting the second parallel test data into the second serial test data is based on the third clock, and
wherein the DUT converting the second serial test data into the second parallel verification data is based on the fourth clock.
7. The tester of claim 6 , wherein the functional module is further configured to:
adjust the first jitter;
receive an adjustment of the first test result responsive to adjusting the first jitter;
generate a characterization result of the first SERDES module based at least on the first test result and the adjustment of the first test result;
adjust the second jitter;
receive an adjustment of the second test result responsive to adjusting the second jitter; and
generate a characterization result of the third SERDES module based at least on the second test result and the adjustment of the first test result,
wherein the characterization results of the first and third SERDES modules are generated concurrently.
8. A method for characterizing a device under test (DUT) comprising first and second serializer/deserializer (SERDES) modules, comprising:
coupling a transmit (TX) output of the first SERDES module to a receive (RX) input of the second SERDES module;
clocking the first SERDES module using a first clock signal;
clocking the second SERDES module using a second clock signal, wherein the first clock signal is equivalent to the second clock signal with a first jitter; and
receiving a first test result from the DUT by configuring the DUT to:
convert, using the first SERDES module based on the first clock, first parallel test data generated by a first test pattern generator comprised in the DUT into first serial test data at the TX output of the first SERDES module, wherein the first serial test data is communicated to the RX input of the second SERDES module via the first conductor;
convert, using the second SERDES module based on the second clock, the first serial test data at the RX input of the second SERDES module into first parallel verification data; and
generate the first test result by analyzing the first parallel verification data based on a first pre-determined criterion using a first test pattern verifier comprised in the DUT.
9. The method of claim 8 ,
wherein analyzing the first parallel verification data based on a first pre-determined criterion is by comparing the first parallel verification data to a delayed version of the first parallel test data,
wherein the first test result comprises a first bit error rate, and
wherein the method further comprising:
adjusting the first jitter;
receiving an adjustment of the first test result responsive to adjusting the first jitter; and
generating a characterization result of the first SERDES module based at least on the first test result and the adjustment of the first test result.
10. The method of claim 8 , the DUT further comprising third and fourth SERDES modules, the method further comprising:
coupling a transmit (TX) output of the third SERDES module to a receive (RX) input of the fourth SERDES module;
receiving a second test result, concurrently with receiving the first test result, from the DUT by further configuring the DUT to:
convert, using the third SERDES module, second parallel test data generated by a second test pattern generator comprised in the DUT into second serial test data at the TX output of the third SERDES module, wherein the second serial test data is communicated to the RX input of the fourth SERDES module via the second conductor;
convert, using the fourth SERDES module, the second serial test data at the RX input of the fourth SERDES module into second parallel verification data; and
generate the second test result, concurrently with generating the first test result, by analyzing the second parallel verification data based on a second pre-determined criterion using a second test pattern verifier comprised in the DUT.
11. The method of claim 9 ,
wherein the first clock generator is further configured to, when the DUT is operatively coupled to the tester, clock the third SERDES module using the first clock signal,
wherein the second clock generator is further configured to, when the DUT is operatively coupled to the tester, clock the fourth SERDES module using the second clock signal,
wherein the DUT converting the second parallel test data into the second serial test data is based on the first clock, and
wherein the DUT converting the second serial test data into the second parallel verification data is based on the second clock.
12. The method of claim 11 further comprising:
adjusting the first jitter;
receiving an adjustment of the first and second test results responsive to adjusting the first jitter; and
generating a characterization result of the first and second SERDES modules concurrently based at least on the first and second test results and the adjustment of the first and second test results.
13. The method of claim 9 , the DUT further comprising third and fourth SERDES modules, the method further comprising:
clocking the third SERDES module using a third clock signal; and
clocking the fourth SERDES module using a fourth clock signal, wherein the third clock signal is equivalent to the fourth clock signal with a second jitter,
wherein the DUT converting the second parallel test data into the second serial test data is based on the third clock, and
wherein the DUT converting the second serial test data into the second parallel verification data is based on the fourth clock.
14. The method of claim 13 further comprising:
adjusting the first jitter;
receiving an adjustment of the first test result responsive to adjusting the first jitter;
generating a characterization result of the first SERDES module based at least on the first test result and the adjustment of the first test result;
adjusting the second jitter;
receiving an adjustment of the second test result responsive to adjusting the second jitter; and
generating a characterization result of the third SERDES module based at least on the second test result and the adjustment of the first test result,
wherein the characterization results of the first and third SERDES modules are generated concurrently.
15. A computer readable medium having instructions for characterizing a device under test (DUT) comprising first and second serializer/deserializer (SERDES) modules, the instructions when executed by a processor comprising functionality for:
coupling a transmit (TX) output of the first SERDES module to a receive (RX) input of the second SERDES module;
clocking the first SERDES module using a first clock signal;
clocking the second SERDES module using a second clock signal, wherein the first clock signal is equivalent to the second clock signal with a first jitter; and
receiving a first test result from the DUT by configuring the DUT to:
convert, using the first SERDES module based on the first clock, first parallel test data generated by a first test pattern generator comprised in the DUT into first serial test data at the TX output of the first SERDES module, wherein the first serial test data is communicated to the RX input of the second SERDES module via the first conductor;
convert, using the second SERDES module based on the second clock, the first serial test data at the RX input of the second SERDES module into first parallel verification data; and
generate the first test result by analyzing the first parallel verification data based on a first pre-determined criterion using a first test pattern verifier comprised in the DUT.
16. The computer readable medium of claim 15 ,
wherein analyzing the first parallel verification data based on a first pre-determined criterion is by comparing the first parallel verification data to a delayed version of the first parallel test data,
wherein the first test result comprises a first bit error rate, and
wherein the method further comprising:
adjusting the first jitter;
receiving an adjustment of the first test result responsive to adjusting the first jitter; and
generating a characterization result of the first SERDES module based at least on the first test result and the adjustment of the first test result.
17. The computer readable medium of claim 15 , the DUT further comprising third and fourth SERDES modules, the instructions when executed by the processor further comprising functionality for:
coupling a transmit (TX) output of the third SERDES module to a receive (RX) input of the fourth SERDES module;
receiving a second test result, concurrently with receiving the first test result, from the DUT by further configuring the DUT to:
convert, using the third SERDES module, second parallel test data generated by a second test pattern generator comprised in the DUT into second serial test data at the TX output of the third SERDES module, wherein the second serial test data is communicated to the RX input of the fourth SERDES module via the second conductor;
convert, using the fourth SERDES module, the second serial test data at the RX input of the fourth SERDES module into second parallel verification data; and
generate the second test result, concurrently with generating the first test result, by analyzing the second parallel verification data based on a second pre-determined criterion using a second test pattern verifier comprised in the DUT.
18. The computer readable medium of claim 17 ,
wherein the first clock generator is further configured to, when the DUT is operatively couple to the tester, clock the third SERDES module using the first clock signal,
wherein the second clock generator is further configured to, when the DUT is operatively couple to the tester, clock the fourth SERDES module using the second clock signal,
wherein the DUT converting the second parallel test data into the second serial test data is based on the first clock, and
wherein the DUT converting the second serial test data into the second parallel verification data is based on the second clock.
19. The computer readable medium of claim 18 , the instructions when executed by the processor further comprising functionality for:
adjusting the first jitter;
receiving an adjustment of the first and second test results responsive to adjusting the first jitter; and
generating a characterization result of the first and second SERDES modules concurrently based at least on the first and second test results and the adjustment of the first and second test results.
20. The computer readable medium of claim 17 , the DUT further comprising third and fourth SERDES modules, the instructions when executed by the processor further comprising functionality for:
clocking the third SERDES module using a third clock signal, wherein the DUT converting the second parallel test data into the second serial test data is based on the third clock;
clocking the fourth SERDES module using a fourth clock signal, wherein the third clock signal is equivalent to the fourth clock signal with a second jitter, wherein the DUT converting the second serial test data into the second parallel verification data is based on the fourth clock;
adjusting the first jitter;
receiving an adjustment of the first test result responsive to adjusting the first jitter;
generating a characterization result of the first SERDES module based at least on the first test result and the adjustment of the first test result;
adjusting the second jitter;
receiving an adjustment of the second test result responsive to adjusting the second jitter; and
generating a characterization result of the third SERDES module based at least on the second test result and the adjustment of the first test result,
wherein the characterization results of the first and third SERDES modules are generated concurrently.