Verification test failure analysis
View Patent ↗Methods and apparatuses are provided that allow for efficient analysis of a graph describing tests, elements of a device design and test results. In various implementations of the invention, a relationship between the elements of a device design, and test results is performed. An entropy value is determined for each corresponding element based upon the test results. The entropy value may assist test engineers in identifying the elements of the device design needing redesign.
1. A computer program product comprising:
software instructions for enabling a computer to perform a set of predetermined operations; and
a computer readable storage device bearing the software instructions;
the set of predetermined operations including:
identifying a verification process performed on an electronic design, wherein the verification process comprises a plurality of tests and a plurality of test results;
identifying a graph, the graph describing a plurality of events, the plurality of tests, and the plurality of test results, wherein at least one of the plurality of test results indicates a failure in the electronic design;
determining an entropy value for ones of the plurality of events, the entropy values based in part upon the plurality of test results;
identifying one or more events that based upon the entropy values contribute to the failure in the electronic design;
making the identified one or more events available to a user; and
making the entropy values available to the user.
2. The product recited in claim 1 , the predetermined operation of determining the entropy values comprising:
generating index values for ones of the plurality of events; and
determining an entropy value for a select event by summing the index values for the select event.
3. The product recited in claim 2 , generating index values for ones of the plurality of events comprises:
determining a probability that ones of the events have a given test result; and
computing the product of the probability and a logarithm of the probability.
4. The product recited in claim 3 , wherein the logarithm is the base 2 logarithm.
5. The product recited in claim 4 , wherein the plurality of events are available states within an electronic device design.
6. The product recited in claim 4 , wherein the plurality of events are functional descriptions within an electronic device design.
7. A computer system comprising:
a processor, and
a memory including instruction executable by the processor that cause the computer system to perform the operations of:
identifying a verification process performed on an electronic design, wherein the verification process comprises a plurality of tests and a plurality of test results;
identifying a graph, the graph describing a plurality of events, the plurality of tests, and the plurality of test results, wherein at least one of the plurality of test results indicates a failure in the electronic design;
determining an entropy value for ones of the plurality of events, the entropy values based in part upon the plurality of test results;
identifying one or more events that based upon the entropy values contribute to the failure in the electronic design;
making the identified one or more events available to a user; and
making the entropy values available to the user.
8. The system recited in claim 7 , the operation of determining the entropy values comprising:
generating index values for ones of the plurality of events; and
determining an entropy value for a select event by summing the index values for the select event.
9. The system recited in claim 8 , generating index values for ones of the plurality of events comprises:
determining a probability that ones of the events have a given test result; and
computing the product of the probability and a logarithm of the probability.
10. The system recited in claim 9 , wherein the logarithm is the base 2 logarithm.
11. The system recited in claim 10 , wherein the plurality of events are available states within an electronic device design.
12. The system recited in claim 10 , wherein the plurality of events are functional descriptions within an electronic device design.
13. A computer implemented method comprising:
causing a processor to execute software instructions that perform a set of functions, the set of functions including;
identifying a verification process performed on an electronic design, wherein the verification process comprises a plurality of tests and a plurality of test results;
identifying a graph, the graph describing a plurality of events, the plurality of tests, and the plurality of test results, wherein at least one of the plurality of test results indicates a failure in the electronic design;
determining an entropy value for ones of the plurality of events, the entropy values based in part upon the plurality of test results;
identifying one or more events that based upon the entropy values contribute to the failure in the electronic design;
making the identified one or more vents available to a user; and
making the entropy values available to the user.
14. The computer implemented method recited in claim 13 , the act of determining the entropy values comprising:
generating index values for ones of the plurality of events; and
determining an entropy value for a select event by summing the index values for the select event.
15. The computer implemented method recited in claim 14 , generating index values for ones of the plurality of events comprises:
determining a probability that ones of the events have a given test result; and
computing the product of the probability and a logarithm of the probability.
16. The computer implemented method recited in claim 15 , wherein the logarithm is the base 2 logarithm.
17. The computer implemented method recited in claim 16 , wherein the plurality of events are available states within an electronic device design.
18. The computer implemented method recited in claim 16 , wherein the plurality of events are functional descriptions within an electronic device design.