IP Library Granted Patent US 8,102,055
Granted Patent B2
US 8,102,055 · App. 12/872,158 · Granted Jan 24, 2012

Semiconductor device

Assignee: Seiko Epson Corporation
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Quick Facts
Patent No.
US 8,102,055
App. No.
12/872,158
Granted
Jan 24, 2012
Kind
B2
Abstract

A semiconductor device including a semiconductor chip, a base substrate, a wiring positioned on the base substrate, and a eutectic alloy. A part of the eutectic alloy is positioned between the wiring and the base substrate.

Claims (24)

1. A semiconductor device, comprising:

a semiconductor chip;

a base substrate;

a wiring that is positioned on the base substrate, a first portion of the wiring having a first surface facing the base substrate, a first part of the first surface of the first portion of the wiring adhering to the base substrate, a second part of the first surface of the first portion of the wiring not being in contact with the base substrate, a tip of the wiring being positioned between the semiconductor chip and the base substrate, a second portion of the wiring being positioned between the first portion of the wiring and the tip of the wiring;

an electrode that is positioned between the wiring and the semiconductor chip, the electrode contacting with the second portion of the wiring; and

an eutectic alloy, a part of the eutectic alloy being positioned between the second part of the first surface of the first portion of the wiring and the base substrate.

2. The semiconductor device according to claim 1 , wherein the first part of the first surface of the first portion of the wiring is positioned in a center of the first surface of the first portion of the wiring.

3. The semiconductor device according to claim 1 , wherein the eutectic alloy is formed avoiding a region overlapping the electrode between the wiring and the base substrate.

4. The semiconductor device according to claim 1 , wherein a plurality of the wirings are positioned on the base substrate.

5. A semiconductor device, comprising:

a semiconductor chip;

a base substrate;

a wiring that is positioned on the base substrate, a first portion of the wiring having a first surface facing the base substrate, an entire surface of the first surface of the first portion of the wiring not being in contact with the base substrate, a tip of the wiring being positioned between the semiconductor chip and the base substrate, a second portion of the wiring being positioned between the first portion of the wiring and the tip of the wiring;

an electrode that is positioned between the wiring and the semiconductor chip, the electrode contacting with the second portion of the wiring; and

an eutectic alloy, a part of the eutectic alloy being positioned between the first surface of the first portion of the wiring and the base substrate.

6. The semiconductor device according to claim 5 , wherein the eutectic alloy is formed avoiding a region overlapping the electrode between the wiring and the base substrate.

7. The semiconductor device according to claim 5 , wherein a plurality of the wirings are positioned on the base substrate.

8. A semiconductor device, comprising:

a semiconductor chip;

a base substrate;

a wiring positioned on the base substrate, a first surface of the wiring facing the base substrate, the first surface of the wiring having a first edge, a second edge opposing the first edge and a central region between the first edge and the second edge, the central region being in contact with the base substrate, the first edge and the second edge not being in contact with the substrate;

an electrode positioned between the wiring and the semiconductor chip; and

an eutectic alloy, a first part of the eutectic alloy being positioned between the first edge and the base substrate, a second part of the eutectic alloy being positioned between the second edge and the base substrate.

9. The semiconductor device according to claim 8 , wherein the eutectic alloy is formed to avoid a region that overlaps the electrode between the wiring and the base substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 2, 2020
From: SEIKO EPSON CORPORATION
To: 138 EAST LCD ADVANCEMENTS LIMITED
Reel/Frame 053671/0900 →
Priority Claims (1)
JP 2005-169340 · Jun 9, 2005 · national
Continuity (3)
Division 12487330 · Jun 18, 2009
Division 11423027 · Jun 8, 2006
Related Publication 20100320615A1 · Dec 23, 2010