Semiconductor device having bar type active pattern
A semiconductor device having a bar type active pattern and a method of manufacturing the same are provided. The semiconductor device may include a semiconductor substrate having a semiconductor fin configured to protrude from a surface of the semiconductor substrate in a first direction, the semiconductor substrate having a first width and a second width crossing the first width, wherein the first width and the second width extend in a second direction. A plurality of active patterns may be arranged in the first direction with a separation gap from the semiconductor fin. A plurality of support patterns may be arranged between the semiconductor fin and one of the plurality of active patterns arranged closer to the semiconductor fin in the first direction, and between the plurality of active patterns arranged in the first direction to support the plurality of active patterns. A gate may be arranged to cross the plurality of active patterns in the second direction and to cover a portion of the at least one of the plurality of active patterns.
1. A semiconductor device comprising:
a semiconductor substrate including a semiconductor fin configured to protrude from a surface of the semiconductor substrate in a first direction, the semiconductor fin having a first width extending in the first direction and a second width crossing the first width in a second direction;
a plurality of active patterns arranged in the first direction with a separation gap from the semiconductor fin;
a plurality of support patterns arranged between the semiconductor fin and one of the plurality of active patterns arranged closest to the semiconductor fin in the first direction, and between the plurality of active patterns arranged in the first direction to support the plurality of active patterns; and
a gate arranged to cross the plurality of active patterns in the second direction and to cover a portion of at least one of the plurality of active patterns,
wherein the plurality of support patterns are insulation patterns.
2. The semiconductor device of claim 1 , wherein the plurality of active patterns are bar type semiconductor patterns that extend in the second direction and have a cross-section with rounded edges.
3. The semiconductor device of claim 2 , wherein the plurality of active patterns are monocrystalline silicon patterns.
4. The semiconductor device of claim 1 , wherein the plurality of support patterns are silicon-germanium-oxide layer patterns.
5. The semiconductor device of claim 1 , further comprising:
an insulation layer arranged between the semiconductor fin and the plurality of support patterns, and between the plurality of support patterns and the plurality of active patterns.
6. The semiconductor device of claim 5 , wherein the insulation layer is a thermal oxide layer.
7. The semiconductor device of claim 1 , wherein the gate has an omega-like shape configured to cover either at least one of the plurality of active patterns or at least one of the plurality of active patterns and a portion of one of the plurality of support patterns that supports the plurality of active patterns in the second direction.
8. The semiconductor device of claim 7 , further comprising:
source and drain regions arranged in portions of the at least one of the plurality of active patterns on both sides of the gate and exposed from the gate; and
a channel region arranged between the source and drain regions.
9. The semiconductor device of claim 8 , wherein widths of the source and drain regions are substantially equal to a width of the channel region in the second direction.
10. The semiconductor device of claim 1 , wherein the gate has a gate all around (GAA) structure configured to cover the plurality of active patterns, the plurality of support patterns supporting the plurality of active patterns, and a portion of the semiconductor fin.
11. The semiconductor device of claim 10 , further comprising:
source and drain regions arranged in portions of the plurality of active patterns and the semiconductor fin that are on both sides of the gate and exposed from the gate; and
multiple channel regions arranged between the source and drain regions.
12. The semiconductor device of claim 11 , wherein widths of the source and drain regions are substantially equal to widths of the multiple channel regions in the second direction.
13. The semiconductor device of claim 12 , wherein the semiconductor substrate further includes a trench on the surface of the semiconductor substrate to define the semiconductor fin, further comprising:
a first insulation layer configured to fill a portion of the trench and exposes at least the exposed portion of the semiconductor fin;
a second insulation layer on the first insulation layer to cover the gate, the plurality of active patterns, the exposed portion of the semiconductor fin and the plurality of support patterns, the second insulation layer including a contact configured to expose portions of the plurality of active patterns and the semiconductor fin that include one of the source and drain regions;
a conductive plug configured to fill the contact and completely cover the exposed portions of the plurality of active patterns and the semiconductor fin; and
a storage electrode connected to the conductive plug.
14. The semiconductor device of claim 13 , further comprising:
a capacitor dielectric layer on the storage electrode and the second insulation layer; and
a plate electrode on the capacitor dielectric layer.
15. The semiconductor device of claim 1 , further comprising:
a gate insulation layer under the gate.