Gray scale drive sequences for pulse width modulated displays
Methods, apparatus, and systems for generating drive sequences for pulse width modulated displays are described. A pulse width modulated signal that includes a drive sequence of temporal segments that are activated and deactivated to produce a desired gray scale. The temporal segments can be non-binary, non-equally weighted. The drive sequence can also include at least two of the temporal segments are least significant bit segments and the other segments are higher order segments.
1. A method for providing a drive sequence for a liquid crystal pulse width modulated display, the method comprising:
determining a set of non-binary, non-equal, weighted temporal segments;
determining at least two least significant bit segments, each comprising at least one lesser segment wherein the at least one lesser segments represent the same lower order significant bit code;
assembling the set of segments into a sequence;
identifying segments in the sequence that are active;
identifying which of the at least two least significant bit segments in the sequence are active; and
using the sequence to pulse width modulate pixels in a display, wherein a pixel's brightness corresponds to the number and temporal weighting of active temporal segments in the sequence.
2. The method of claim 1 , wherein higher order segments increase in weighting monotonically.
3. The method of claim 1 , wherein the weighting of the segments is adjusted to produce a gray scale output corresponding to the number of active segments in the sequence that simulates a gamma curve.
4. The method of claim 1 , wherein the at least two least significant bit segments are not temporally adjacent to each other.
5. The method of claim 1 , wherein the temporal activation of the segments is discontinuous.
6. The method of claim 1 , wherein the sequence comprises non-contiguous time slots.
7. A liquid crystal display comprising:
a plurality of pixels;
a voltage controller that provides at least one voltage supply that is applied to the pixels in the display; and
a processor that receives image data and determines a set of non-binary, non-equal, weighted temporal segments and at least two least significant bit segments each comprising at least one lesser segment wherein the at least one lesser segments represent the same lower order significant bit code, based on the image data, and assembles the set of segments into a sequence, wherein selected segments are activated in accordance with a desired brightness level of pixels within the display.
8. The display of claim 7 , wherein higher order segments increase in weighting monotonically.
9. The display of claim 7 , wherein the at least two least significant bit segments are not adjacent to each other.
10. The display of claim 7 , wherein the temporal activation of the segments is discontinuous,
11. The display of claim 7 , wherein the sequence comprises non-contiguous time slots.
12. The display of claim 7 , wherein the pixels comprise liquid crystal on silicon elements.
13. The display of claim 7 , wherein the image data comprises a gray scale command.
14. The display of claim 7 , wherein the image data comprises multiple color image data.
15. A controller for a pulse width modulated liquid crystal display, the controller comprising:
a voltage controller that provides at least one voltage supply that is applied to pixels in a display; and
a processor that receives image data and determines a set of non-binary, non-equal, weighted temporal segments based on the image data, and at least two least significant bit segments, each comprising at least one lesser segment wherein the at least one lesser segments represent the same lower order significant bit code, and assembles the set of segments into a sequence, wherein selected segments are activated in accordance with a desired brightness level of pixels within the display.
16. The controller of claim 15 , wherein higher order segments increase in weighting monotonically.
17. The controller of claim 15 , wherein the at least two least significant bit segments are not adjacent to each other.
18. The controller of claim 15 , wherein the temporal activation of the segments is discontinuous.
19. The controller of claim 15 , wherein the sequence comprises non-contiguous time slots.
20. The controller of claim 15 , wherein the pixels comprise liquid crystal on silicon elements.
21. The controller of claim 15 , wherein the image data comprises a gray scale command.
22. The controller of claim 15 , wherein the image data comprises multiple color image data.
23. The method of claim 1 , wherein the at least two least significant bit segments comprise a first least significant bit sequence and a second least significant bit sequence.
24. The method of claim 23 , wherein the first least significant bit sequence is of substantially identical temporal weighting to the second least significant bit sequence.
25. The method of claim 23 , wherein the first least significant bit sequence differs in temporal weighting from the second least significant bit sequence.
26. The display of claim 7 , wherein the received image data is digital data.
27. The display of claim 7 , wherein the at least two least significant bit segments comprise a first least significant bit sequence and a second least significant bit sequence.
28. The display of claim 27 , wherein the first least significant bit sequence is of substantially identical temporal weighting to the second least significant bit sequence.
29. The display of claim 27 , wherein the first least significant bit sequence differs in temporal weighting from the second least significant bit sequence.
30. The controller of claim 15 , wherein the received image data is digital data.
31. The controller of claim 15 , wherein the at least two least significant bit segments comprise a first least significant bit sequence and a second least significant bit sequence.
32. The controller of claim 31 , wherein the first least significant bit sequence is of substantially identical temporal weighting to the second least significant bit sequence.
33. The controller of claim 31 , wherein the first least significant bit sequence differs in temporal weighting from the second least significant bit sequence.
34. The method of claim 1 , wherein a first least significant bit sequence has a different number of lesser segments than a second least significant bit sequence.
35. The method of claim 34 , wherein any lesser segments not represented in both least significant bit segments remain active.
36. The display of claim 7 , wherein a first least significant bit sequence has a different number of lesser segments than a second least significant bit sequence.
37. The display of claim 36 , wherein any lesser segments not represented in both least significant bit segments remain active.
38. The controller of claim 15 , wherein a first least significant bit sequence has a different number of lesser segments than a second least significant bit sequence.
39. The controller of claim 38 , wherein any lesser segments not represented in both least significant bit segments remain active.