IP Library Granted Patent US 8,115,568
Granted Patent B2
US 8,115,568 · App. 12/190,597 · Granted Feb 14, 2012

Layout of a circuit board with stacked signal and reference layers and an opening in the reference layer

Assignee: Compal Electronics, Inc.
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Quick Facts
Patent No.
US 8,115,568
App. No.
12/190,597
Granted
Feb 14, 2012
Kind
B2
Abstract

A layout of a circuit board includes a first signal layer, a second signal layer, and a third signal layer. The first signal layer has a transmission line. The second signal layer is stacked below the first signal layer, and has an opening. The third signal layer is stacked below the first and second signal layers with the second signal layer sandwiched between the first and third signal layers. The third signal layer is electrically connected to the second signal layer, and both of the second and third signal layers are ground layers or power layers. An orthogonal projection of a segment of the transmission line on the third signal layer is overlapped with that of the opening on the third signal layer. Therefore, an equivalent impedance of the segment of the transmission line with respect to the second and third signal layers can be increased or decreased.

Claims (9)

1. A layout of a circuit board, comprising:

a first signal layer, comprising a transmission line;

a reference layer, stacked below the first signal layer, and comprising an opening; and

a second signal layer, stacked below the first signal layer and the reference layer with the reference layer sandwiched between the first and second signal layers, wherein the second signal layer further includes a reference line, set on the same level as the second signal layer, and being electrically and directly connected to the reference layer, and an orthogonal projection of a segment of the transmission line on the reference line is overlapped with an orthogonal projection of the opening on the reference line.

2. The layout of a circuit board according to claim 1 , wherein a width of the orthogonal projection of the segment of the transmission line on the reference line is smaller than a width of the orthogonal projection of the opening on the reference line.

3. The layout of a circuit board according to claim 1 , wherein an equivalent impedance of the segment of the transmission line is greater than an equivalent impedance of any other segment of the transmission line.

4. The layout of a circuit board according to claim 1 , wherein the reference line is connected to the reference layer through a conductive via.

5. The layout of a circuit board according to claim 1 , wherein the reference layer is a ground layer.

6. The layout of a circuit board according to claim 1 , wherein the reference layer is a power layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2008
From: HSU, TI-MING
To: COMPAL ELECTRONICS, INC.
Reel/Frame 021419/0913 →
Priority Claims (1)
TW 96135143 A · Sep 20, 2007 · national
Continuity (1)
Related Publication 20090079523A1 · Mar 26, 2009