Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device comprising:

a stacked body with a plurality of dielectric films and electrode films alternately stacked therein, the electrode film being divided into a plurality of control gate electrodes extending in one direction;

a plurality of select gate electrodes provided on the stacked body and extending in the one direction;

a plurality of semiconductor pillars extending in a stacking direction of the stacked body and penetrating through the control gate electrodes and the select gate electrode;

a plurality of source lines extending in the one direction and connected to an upper end portion of a subset of the semiconductor pillars;

a plurality of bit lines extending in a direction crossing the one direction and connected to an upper end portion of the remaining semiconductor pillars;

a connecting member interconnecting between a lower end portion of one of the semiconductor pillars with the upper end portion connected to the source line and a lower end portion of another of the semiconductor pillars with the upper end portion connected to the bit line;

a charge storage layer provided between the control gate electrode and the semiconductor pillar; and

a gate dielectric film provided between the select gate electrode and the semiconductor pillar,

a different potential being applicable to uppermost one of the control gate electrodes than that applied to the other control gate electrodes.

2. The memory device according to claim 1 , wherein in operation of programming data, an intermediate potential between a potential of the select gate electrode penetrated by the same semiconductor pillar as the uppermost control gate electrode and a potential of the other control gate electrodes penetrated by the same semiconductor pillar as the uppermost control gate electrode is applied to the uppermost control gate electrode.

3. The memory device according to claim 2 , wherein in the stacking direction of the stacked body, a distance between the select gate electrode and the uppermost control gate electrode is less than or equal to a distance between the control gate electrodes.

4. The memory device according to claim 1 , wherein in operation of programming data, a potential between a potential applied to the select gate electrode of a non-selected memory string and a potential applied to the control gate electrode of a memory cell to be programmed with the data is applied to the uppermost control gate electrode.

5. The memory device according to claim 4 , wherein in the stacking direction of the stacked body, a distance between the select gate electrode and the uppermost control gate electrode is less than or equal to a distance between the control gate electrodes.

6. The memory device according to claim 1 , wherein in the stacking direction of the stacked body, a distance between the select gate electrode and the uppermost control gate electrode is less than or equal to a distance between the control gate electrodes.

7. The memory device according to claim 1 , wherein a lower portion of a pair of the interconnected semiconductor pillars and the connecting member are integrally formed from the same material.

8. The memory device according to claim 1 , wherein the two semiconductor pillars interconnected by the connecting member penetrate through different ones of the control gate electrodes and are adjacent in the crossing direction, and the two semiconductor pillars not interconnected by the connecting member penetrate through a common one of the control gate electrodes.

9. A nonvolatile semiconductor memory device comprising:

a stacked body with a plurality of dielectric films and electrode films alternately stacked therein, the electrode film being divided into a plurality of control gate electrodes extending in one direction;

a plurality of select gate electrodes provided on the stacked body and extending in the one direction;

a plurality of semiconductor pillars extending in a stacking direction of the stacked body and penetrating through the control gate electrodes and the select gate electrode;

a plurality of source lines extending in the one direction and connected to an upper end portion of a subset of the semiconductor pillars;

a plurality of bit lines extending in a direction crossing the one direction and connected to an upper end portion of the remaining semiconductor pillars;

a connecting member interconnecting between a lower end portion of one of the semiconductor pillars with the upper end portion connected to the source line and a lower end portion of another of the semiconductor pillars with the upper end portion connected to the bit line;

a charge storage layer provided between the control gate electrode and the semiconductor pillar;

a gate dielectric film provided between the select gate electrode and the semiconductor pillar;

a first potential generation circuit configured to apply a control potential to the control gate electrodes other than the uppermost one of the control gate electrodes; and

a second potential generation circuit configured to apply a different potential to the uppermost control gate electrode than the control potential.

10. The memory device according to claim 9 , wherein in operation of programming data, an intermediate potential between a potential of the select gate electrode penetrated by the same semiconductor pillar as the uppermost control gate electrode and a potential of the other control gate electrodes penetrated by the same semiconductor pillar as the uppermost control gate electrode is applied to the uppermost control gate electrode.

11. The memory device according to claim 9 , wherein in the stacking direction of the stacked body, a distance between the select gate electrode and the uppermost control gate electrode is less than or equal to a distance between the control gate electrodes.

12. The memory device according to claim 9 , wherein in operation of programming data, a potential between a potential applied to the select gate electrode of a non-selected memory string and a potential applied to the control gate electrode of a memory cell to be programmed with the data is applied to the uppermost control gate electrode.

13. The memory device according to claim 12 , wherein in the stacking direction of the stacked body, a distance between the select gate electrode and the uppermost control gate electrode is less than or equal to a distance between the control gate electrodes.

14. The memory device according to claim 9 , wherein in the stacking direction of the stacked body, a distance between the select gate electrode and the uppermost control gate electrode is less than or equal to a distance between the control gate electrodes.

15. The memory device according to claim 9 , wherein a lower portion of a pair of the interconnected semiconductor pillars and the connecting member are integrally formed from the same material.

16. The memory device according to claim 9 , wherein the two semiconductor pillars interconnected by the connecting member penetrate through different ones of the control gate electrodes and are adjacent in the crossing direction, and the two semiconductor pillars not interconnected by the connecting member penetrate through a common one of the control gate electrodes.

17. The memory device according to claim 9 , further comprising:

a semiconductor substrate including a memory cell formation region and a peripheral circuit region,

the stacked body being placed in the memory cell formation region, and

the first potential generation circuit and the second potential generation circuit being placed in the peripheral circuit region.