Strain enhanced semiconductor devices and methods for their fabrication
A strain enhanced semiconductor device and methods for its fabrication are provided. One method comprises embedding a strain inducing semiconductor material in the source and drain regions of the device to induce a strain in the device channel. Thin metal silicide contacts are formed to the source and drain regions so as not to relieve the induced strain. A layer of conductive material is selectively deposited in contact with the thin metal silicide contacts, and metallized contacts are formed to the conductive material.
1. A method for manufacturing a strain enhanced semiconductor device comprising a semiconductor substrate, the semiconductor substrate having a surface and comprising source and drain regions formed therein that are separated by a channel region formed in the semiconductor substrate, and the semiconductor device further comprising a gate electrode overlying the surface and the channel region of the semiconductor substrate, the method comprising the steps of:
forming recesses in the semiconductor substrate;
epitaxially growing a strain inducing semiconductor material in the recesses to embed the strain inducing semiconductor material in the source and drain regions;
depositing a layer of silicide forming metal on substantially planar surfaces of the strain inducing semiconductor material that is embedded in the source and drain regions and heating to form thin metal silicide contacts directly along the substantially planar surfaces of the strain inducing semiconductor material that is embedded in the source and drain regions;
electro-lessly depositing a seed layer comprising palladium overlying the substantially planar surfaces of the strain inducing semiconductor material that is embedded in the source and drain regions, wherein the seed layer is in physical contact with the thin metal silicide contacts;
electro-lessly depositing a conductive layer comprising cobalt and tungsten overlying the seed layer;
then, without removing any of the conductive layer, depositing an insulating layer overlying the conductive layer;
etching contact openings through the insulating layer; and
forming, in the contact openings, metallized contacts that physically contact the conductive layer.
2. The method of claim 1 further comprising a step of depositing a layer of stressed insulating material overlying the gate electrode.
3. The method of claim 2 wherein the step of depositing the layer of stressed insulating material comprises a step of depositing a layer of stressed silicon nitride.
4. The method of claim 1 wherein the semiconductor device comprises a PMOS transistor and wherein the step of epitaxially growing the strain inducing semiconductor material comprises the step of epitaxially growing silicon germanium in the recesses to embed the silicon germanium in the source and drain regions.
5. The method of claim 1 wherein the semiconductor device comprises an NMOS transistor and wherein the step of epitaxially growing the strain inducing semiconductor material comprises the step of epitaxially growing silicon carbide in the recesses to embed the silicon carbide in the source and drain regions.
6. The method of claim 1 wherein the step of depositing the layer of silicide forming metal, comprises:
depositing the layer of silicide forming metal on the substantially planar surfaces of the strain inducing semiconductor material that is embedded in the source and drain regions and on a surface of the gate electrode, and heating to form the thin metal silicide contacts directly along the substantially planar surfaces of the strain inducing semiconductor material that is embedded in the source and drain regions and to form a first thin metal silicide contact along the surface of the gate electrode.
7. The method of claim 6 wherein the step of depositing the insulating layer overlying the conductive layer, comprises:
depositing the insulating layer directly overlying and directly contacting the conductive layer and directly contacting the first thin metal silicide contact along the surface of the gate electrode.
8. The method of claim 1 , wherein the step of forming, in the contact openings, the metallized contacts that physically contact the conductive layer, comprises:
forming, in the contact openings, the metallized contacts that extend through the insulating layer and that physically contact the conductive layer.
9. The method of claim 1 , wherein the step of then, without removing any of the conductive layer, depositing the insulating layer overlying the conductive layer, comprises:
then, following the step of electro-lessly depositing the conductive layer and without removing any of the conductive layer, depositing the insulating layer directly overlying and directly contacting the conductive layer.
10. The method of claim 9 , wherein the step of etching the contact openings through the insulating layer, comprises:
etching the contact openings through the insulating layer that extend to a surface of the conductive layer.
11. A method for manufacturing a strain enhanced semiconductor device comprising a semiconductor substrate, the semiconductor substrate having a surface and comprising source and drain regions formed therein that are separated by a channel region formed in the semiconductor substrate, and the semiconductor device further comprising a gate electrode overlying the surface and the channel region of the semiconductor substrate, the method comprising the steps of:
forming recesses in the semiconductor substrate;
epitaxially growing a strain inducing semiconductor material in the recesses to embed the strain inducing semiconductor material in the source and drain regions;
depositing a layer of silicide forming metal on substantially planar surfaces of the strain inducing semiconductor material that is embedded in the source and drain regions and on a surface of the gate electrode, and heating to form thin metal silicide contacts directly along the substantially planar surfaces of the strain inducing semiconductor material that is embedded in the source and drain regions and to form a first thin metal silicide contact along the surface of the gate electrode;
electro-lessly depositing a seed layer comprising palladium overlying the substantially planar surfaces of the strain inducing semiconductor material that is embedded in the source and drain regions, wherein the seed layer is in physical contact with the thin metal silicide contacts;
electro-lessly depositing a conductive layer comprising cobalt and tungsten overlying the seed layer;
then, following the step of electro-lessly depositing the conductive layer and without removing any of the conductive layer, depositing an insulating layer directly contacting the conductive layer and directly contacting the first thin metal silicide contact along the surface of the gate electrode;
etching contact openings through the insulating layer; and
forming, in the contact openings, metallized contacts that extend through the insulating layer and physically contact the conductive layer.
12. The method of claim 11 , wherein the step of depositing the insulating layer comprises:
then, following the step of electro-lessly depositing the conductive layer and without removing any of the conductive layer, depositing the insulating layer directly overlying and directly contacting the conductive layer and directly contacting the first thin metal silicide contact along the surface of the gate electrode.
13. The method of claim 12 , wherein the step of etching the contact openings through the insulating layer, comprises:
etching the contact openings through the insulating layer that extend to a surface of the conductive layer.