Three-dimensional semiconductor device
View Patent ↗A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.
1. A semiconductor device, comprising:
a first active area formed on a first semiconductor substrate;
a second active area formed on a second semiconductor substrate; and
a redundant bonding-conductor structure coupling the first active area and the second active area, the redundant bonding-conductor structure extending through the second semiconductor substrate, the redundant bonding-conductor comprising:
at least two vias extending through the second semiconductor substrate, the at least two vias being electrically coupled together.
2. The semiconductor device of claim 1 , wherein the redundant bonding-conductor structure comprises at least two pads on a surface of the second semiconductor substrate, the two pads being electrically coupled together.
3. The semiconductor device of claim 1 , wherein the redundant bonding-conductor structure is formed of a metal alloy.
4. The semiconductor device of claim 3 , wherein the alloy comprises copper (Cu).
5. The semiconductor device of claim 3 , wherein the alloy comprises tungsten (W).
6. The semiconductor device of claim 3 , wherein the alloy comprises aluminum (Al).
7. The semiconductor device of claim 1 , wherein at least one via of the redundant bonding-conductor structure has a substantially circular cross-section.
8. The semiconductor device of claim 1 , wherein at least one via of the redundant bonding-conductor structure has a non-circular cross-section.
9. The semiconductor device of claim 8 , wherein the at least one via comprises a vertical dimension that is greater than or equal to about five times the greatest via horizontal dimension.
10. The semiconductor device of claim 1 , further comprising a plurality of redundant bonding-conductor structures, each passing completely through the second semiconductor substrate.
11. The semiconductor device of claim 1 , further comprising a third active area on a third semiconductor substrate and at least one redundant bonding-conductor structure passing completely through the third semiconductor substrate and coupling the third active area to a fourth active area formed on the second substrate.
12. A conductor structure for coupling a component on a first semiconductor chip to a component on a second semiconductor chip, the first semiconductor chip and the second semiconductor chip being assembled in a stacked configuration, the conductor structure comprising:
a first conductive pad on a first surface of the second semiconductor chip;
a first conductive via extending from the first conductive pad to a second surface of the second semiconductor chip; and
a second conductive via extending to the second surface of the second semiconductor chip and electrically coupled to the first conductive via;
wherein the conductor structure is a redundant bonding-conductor structure extending to a bonding surface of the first semiconductor chip.
13. A 3D semiconductor chip assembly, comprising:
a first chip comprising a first active area;
a second chip comprising a second active area and positioned above the first chip; and
a redundant bonding-conductor structure coupling the first active area to the second active area, the redundant bonding-conductor comprising:
at least two conductive vias extending through the second chip, the at least two conductive vias being electrically coupled together.
14. The 3D semiconductor chip assembly of claim 13 , wherein the first chip and the second chip are bonded together using a bonding material.
15. The 3D semiconductor chip assembly of claim 13 , further comprising a third chip comprising a third active area and a second redundant-conductor bonding structure coupling the third active area to a fourth active area on one of the first chip or the second chip.
16. The 3D semiconductor chip assembly of claim 15 , wherein the fourth active area is not the first active area and is not the second active area.
17. The 3D semiconductor chip assembly of claim 13 , wherein the second chip is mounted in a face-up orientation.
18. The 3D semiconductor chip assembly of claim 13 , wherein the second chip is mounted in a face-down orientation.