IP Library Granted Patent US 8,138,048
Granted Patent B2
US 8,138,048 · App. 12/704,012 · Granted Mar 20, 2012

Semiconductor storage device

Assignee: Unisantis Electronics Singapore Pte Ltd.
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Quick Facts
Patent No.
US 8,138,048
App. No.
12/704,012
Granted
Mar 20, 2012
Kind
B2
Abstract

It is intended to provide a semiconductor device having a reduced thickness of a silicon nitride film on an outer periphery of a gate electrode of an SGT. A semiconductor device of the present invention is constructed using a MOS transistor which has a structure where a drain, a gate and a source are arranged in a vertical direction with respect to a substrate, and the gate is formed to surround a pillar-shaped semiconductor layer. The semiconductor device comprises: a silicide layer formed in an upper surface of each of upper and lower diffusion layers formed in upper and underneath portions of the pillar-shaped semiconductor layer, in a self-alignment manner, wherein the silicide layer is formed after forming a first dielectric film on a sidewall of the pillar-shaped semiconductor layer to protect the sidewall of the pillar-shaped semiconductor layer during formation of the silicide layer; and a second dielectric film formed, after forming the silicide layer and then removing the first dielectric film, in such a manner as to cover a source/drain region formed in the underneath portion of the pillar-shaped semiconductor layer, the gate electrode formed on the sidewall of the pillar-shaped semiconductor layer, and a source/drain region formed on the upper portion of the pillar-shaped semiconductor layer.

Claims (13)

1. A method of producing a semiconductor device constructed using a MOS transistor which has a structure where a source region and a drain region are formed, respectively, in one and a remaining one of an upper portion and an underneath portion of a pillar-shaped semiconductor layer formed on a silicon substrate, and a gate electrode is formed to surround the pillar-shaped semiconductor layer, the method being characterized by comprising the steps of:

etching a silicon substrate to form a pillar-shaped semiconductor layer;

forming a gate dielectric film at least on a surface of a sidewall of the pillar-shaped semiconductor layer;

forming a gate conductive film on a surface of the gate dielectric film;

etching each of the gate dielectric film and the gate conductive film to form a gate electrode;

forming a first dielectric film on the sidewall of the upper portion of the pillar-shaped semiconductor layer to prevent siliciding the sidewall of the upper portion of the pillar-shaped semiconductor layer when a silicide layer is formed on an exposed portion of each of the source and drain regions formed in the upper and underneath portions of the pillar-shaped semiconductor layer;

forming a silicide layer on the exposed portion of each of the diffusion layers formed in the upper and underneath portions of the pillar-shaped semiconductor layer;

after completion of the formation of the silicide layer, removing the first dielectric film;

forming a second dielectric film on the pillar-shaped semiconductor layer and the gate electrode to serve as a contact stopper; and

forming a third dielectric film on the second dielectric film to serve as an interlayer film.

2. The method as defined in claim 1 , wherein the first dielectric film comprises any one of a silicon oxide film, a silicon nitride film or a stacked layer consisting of the silicon oxide film and the silicon nitride film.

3. The method as defined in claim 1 , wherein the second dielectric film comprises a silicon nitride film and the third dielectric film comprises a silicon oxide film.

4. The method as defined in claim 2 , wherein the second dielectric film comprises a silicon nitride film and the third dielectric film comprises a silicon oxide film.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2011
From: UNISANTIS ELECTRONICS JAPAN LTD.
To: UNISANTIS ELECTRONICS SINGAPORE PTE LTD.
Reel/Frame 026970/0670 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2010
From: MASUOKA, FUJIO; ARAI, SHINTARO
To: UNISANTIS ELECTRONICS (JAPAN) LTD.
Reel/Frame 024301/0744 →
Priority Claims (1)
WO PCT/JP2008/061308 · Jun 20, 2008 · international
Continuity (3)
Continuation PCTJP2009061293 · Jun 22, 2009
Provisional Application 61207553 · Feb 13, 2009
Related Publication 20100203714A1 · Aug 12, 2010