Integrated alignment and overlay mark
An integrated alignment and overlay mark includes a pre-layer pattern for reticle-to-wafer registration implemented in an exposure tool, and a current-layer pattern incorporated with the pre-layer pattern. The pre-layer pattern and the current-layer pattern constitute an overlay mark for determining registration accuracy between two patterned layers on a semiconductor wafer.
1. An integrated alignment and overlay mark, comprising:
a pre-layer pattern for reticle-to-wafer registration implemented in an exposure tool, wherein the pre-layer pattern comprises a plurality of sets of slits or bars, and wherein at least two slits or bars of each set that are closest to a center of the integrated alignment and overlay mark are within a laser spot area; and
a current-layer pattern incorporated with said pre-layer pattern, said pre-layer pattern and said current-layer pattern constitute an overlay mark for determining registration accuracy between two patterned layers on a semiconductor wafer.
2. The integrated alignment and overlay mark according to claim 1 wherein said pre-layer pattern and said current-layer pattern are both formed in a kerf region.
3. The integrated alignment and overlay mark according to claim 1 wherein said pre-layer pattern and said current-layer pattern are both formed within an active circuit die area.
4. The integrated alignment and overlay mark according to claim 1 wherein said pre-layer pattern comprises a plurality of sets of slits.
5. The integrated alignment and overlay mark according to claim 4 wherein said plurality of sets of slits are arranged in a box shape thereby forming a rectangular pre-layer pattern.
6. The integrated alignment and overlay mark according to claim 4 wherein each of said slits has a line width L, and has a space S between two adjacent said slits, wherein the line width to space (L:S) ratio is about 1:3.
7. The integrated alignment and overlay mark according to claim 1 wherein said current-layer pattern is disposed in a central region of the pre-layer pattern.
8. The integrated alignment and overlay mark according to claim 1 wherein said integrated alignment and overlay mark has a dimension of about 40 μm×40 μm.
9. The integrated alignment and overlay mark according to claim 1 wherein said integrated alignment and overlay mark has a dimension of smaller than 40 μm×40 μm.
10. The integrated alignment and overlay mark according to claim 1 wherein said pre-layer pattern is formed in a first material layer on the semiconductor wafer.
11. The integrated alignment and overlay mark according to claim 10 wherein a second material layer is deposited over the first material layer, and said current-layer pattern is formed in a photoresist layer coated on said second material layer.
12. An integrated alignment and overlay mark, comprising:
a semiconductor wafer having thereon a first material layer and a second material layer overlying said first material layer;
an alignment mark defined in said first material layer for reticle-to-wafer registration implemented in an exposure tool, wherein the alignment mark comprises a plurality of sets of slits or bars, and wherein at least two slits or bars of each set that are closest to a center of the integrated alignment and overlay mark are within a laser spot area; and
an overlay mark incorporating said alignment mark with a current-layer pattern defined in a photoresist layer on said second material layer.
13. The integrated alignment and overlay mark according to claim 12 wherein said integrated alignment and overlay mark is disposed in a kerf region.
14. The integrated alignment and overlay mark according to claim 12 wherein said integrated alignment and overlay mark is disposed within an active circuit die area.
15. The integrated alignment and overlay mark according to claim 12 wherein said alignment mark consists of a plurality of sets of slits.
16. The integrated alignment and overlay mark according to claim 15 wherein said plurality of sets of slits are arranged in a box shape.
17. The integrated alignment and overlay mark according to claim 15 wherein each of said slits has a line width L, and has a space S between two adjacent said slits, wherein the line width to space (L:S) ratio is about 1:3.
18. The integrated alignment and overlay mark according to claim 12 wherein said current-layer pattern is disposed in a central region of the alignment mark.
19. The integrated alignment and overlay mark according to claim 12 wherein said integrated alignment and overlay mark has a dimension of about 40 μm×40 μm.
20. The integrated alignment and overlay mark according to claim 12 wherein said integrated alignment and overlay mark has a dimension of smaller than 40 μm×40 μm.