Enhanced efficiency low-dropout linear regulator and corresponding method
View Patent ↗A low-dropout linear regulator includes an error amplifier which includes a cascaded arrangement of a differential amplifier and a gain stage. The gain stage includes a transistor driven by the differential amplifier to produce at a drive signal for an output stage of the regulator. The transistor is interposed over its source-drain line between a first resistive load included in a RC network creating a zero in the open loop gain of the regulator, and a second resistive load to produce a drive signal for the output stage of the regulator. The second resistive load is a non-linear compensation element to render current consumption linearly proportional to the load current to the regulator. The first resistive load is a non-linear element causing the frequency of said zero created by the RC network to decrease as the load current of the regulator decreases.
1. A low-dropout linear regulator comprises:
an error amplifier including a cascaded arrangement of a differential amplifier and a gain stage, said gain stage including at least one transistor driven by said differential amplifier to produce at least one drive signal for an output stage of the regulator, wherein said at least one transistor is interposed over its source-drain line between
at least one first resistive load included in a RC network creating a zero in the open loop gain of the regulator, and
at least one second resistive load to produce at least one drive signal for an output stage of the regulator,
wherein said at least one second resistive load is a non-linear compensation element to render current consumption linearly proportional to the load current to the regulator, and said at least one first resistive load is a non-linear element causing the frequency of said zero created by said RC network to decrease as the load current of the regulator decreases, and wherein said current consumption is made linearly proportional to the load current to the regulator without adversely affecting regulator stability.
2. The regulator of claim 1 , wherein at least one of said non-linear resistive loads is a diode.
3. The regulator of claim 2 , wherein at least one of said non-linear resistive loads is transistor connected as a diode.
4. The regulator of claim 3 , further comprising:
a level shifter interposed between said differential amplifer and said gain stage to increase the level of the drive of said at least one transistor by said differential amplifier.
5. The regulator of claim 3 , wherein said differential amplifier includes an adaptive bias to decrease the quiescent current at low output currents of the regulator.
6. The regulator of claim 3 , wherein said output stage includes a small power section and a large power section, said gain stage includes two drivers selectively activatable to drive said small power section and said large power section, respectively, of said output stage, and wherein, in each of said two drivers,
a transistor is provided driven by said differential amplifier to produce a respective drive signal for either of said small power section and said large power section of said output stage of the regulator,
said transistor is interposed over its source-drain line between a first resistive load included in a RC network creating a zero in the open loop gain of the regulator, and a second resistive load to produce said respective drive signal for either of said small power section and said large power section of said output stage of the regulator,
both said first resistive load and said second resistive load are a non-linear compensation elements whereby current consumption is made linearly proportional to the load current to the regulator without adversely affecting regulator stability.
7. The regulator of claim 2 , further comprising:
a level shifter interposed between said differential amplifer and said gain stage to increase the level of the drive of said at least one transistor by said differential amplifier.
8. The regulator of claim 2 , wherein said differential amplifier includes an adaptive bias to decrease the quiescent current at low output currents of the regulator.
9. The regulator of claim 2 , wherein said output stage includes a small power section and a large power section, said gain stage includes two drivers selectively activatable to drive said small power section and said large power section, respectively, of said output stage, and wherein, in each of said two drivers,
a transistor is provided driven by said differential amplifier to produce a respective drive signal for either of said small power section and said large power section of said output stage of the regulator,
said transistor is interposed over its source-drain line between a first resistive load included in a RC network creating a zero in the open loop gain of the regulator, and a second resistive load to produce said respective drive signal for either of said small power section and said large power section of said output stage of the regulator,
both said first resistive load and said second resistive load are a non-linear compensation elements whereby current consumption is made linearly proportional to the load current to the regulator without adversely affecting regulator stability.
10. The regulator of claim 1 , further comprising:
a level shifter interposed between said differential amplifer and said gain stage to increase the level of the drive of said at least one transistor by said differential amplifier.
11. The regulator of claim 1 , wherein said differential amplifier includes an adaptive bias to decrease the quiescent current at low output currents of the regulator.
12. The regulator of claim 1 , wherein said output stage includes a small power section and a large power section, said gain stage includes two drivers selectively activatable to drive said small power section and said large power section, respectively, of said output stage, and wherein, in each of said two drivers,
a transistor is provided driven by said differential amplifier to produce a respective drive signal for either of said small power section and said large power section of said output stage of the regulator,
said transistor is interposed over its source-drain line between a first resistive load included in a RC network creating a zero in the open loop gain of the regulator, and a second resistive load to produce said respective drive signal for either of said small power section and said large power section of said output stage of the regulator,
both said first resistive load and said second resistive load are a non-linear compensation elements whereby current consumption is made linearly proportional to the load current to the regulator without adversely affecting regulator stability.
13. A method of operating a low-dropout linear regulator including an error amplifier including a cascaded arrangement of a differential amplifier and a gain stage, including driving at least one transistor in said gain stage by means of said differential amplifier to produce at least one drive signal for an output stage of the regulator, wherein said at least one transistor is interposed over its source-drain line between:
at least one first resistive load included in a RC network creating a zero in the open loop gain of the regulator, and
at least one second resistive load to produce at least one drive signal for an output stage ( 106 ) of the regulator, wherein said at least one second (M 2 ) resistive load is a non-linear compensation element to render current consumption linearly proportional to the load current to the regulator,
the method including making also said at least one first resistive load a non-linear element causing and cause the frequency of said zero created by said RC network to decrease as the load current of the regulator decreases, whereby current consumption is made linearly proportional to the load current to the regulator without adversely affecting regulator stability.