IP Library Granted Patent US 8,154,749
Granted Patent B2
US 8,154,749 · App. 12/092,404 · Granted Apr 10, 2012

Image signal processor and deferred vertical synchronous signal outputting method

Assignee: Mtekvision Co., Ltd.
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Quick Facts
Patent No.
US 8,154,749
App. No.
12/092,404
Granted
Apr 10, 2012
Kind
B2
Abstract

A method of transferring a deferred vertical synchronous signal and an image signal processor executing the method thereof are disclosed. Once the vertical synchronous signal for a k th frame is inputted from an encoding unit after a capture command is inputted, the method transmits a defer control command for a (k+1) th frame to an image sensor. Then, a return control command is transmitted to the image sensor if encoding of the k th frame is completed. With the present invention, complete encoding of image data becomes possible.

Claims (39)

1. An imaging device comprising:

an image sensor, outputting an electrical signal corresponding to an external image;

a sub-ISP (Image Signal Processor), executing a pre-process corresponding to any one of filtering and interpolation of the electrical signal;

an encoding unit, generating encoded image data by encoding in accordance with the pre-processed electrical signal; and

a data output unit, outputting the encoded image data to a receiving part,

whereas the sub-ISP outputs to the image sensor a defer control command for expanding an output section of a vertical synchronous signal corresponding to a (k+1) th frame following a k th frame to be processed after an input of a capture command, k being a natural number, and the image sensor expands the output section of the vertical synchronous signal and outputs the vertical synchronous signal in accordance with the defer control command.

2. The imaging device of claim 1 , wherein an end point of the output section of the vertical synchronous signal outputted from the image sensor coincides with or is outputted following a point at which encoding of the k th frame is completed by the encoding unit, and the end point is either a falling edge or a rising edge.

3. The imaging device of claim 1 , wherein, once the data output unit detects and notifies to the sub-ISP that encoding of the k th frame is completed, the sub-ISP outputs a return control command to the image sensor,

whereas the return control command resets to a default a length of an output section of a vertical synchronous signal corresponding to a (k+2) th frame, and readjusts a gain value to a default.

4. The imaging device of claim 1 , wherein the encoded image data outputted for the k th frame is between “START MARKER” and “STOP MARKER”.

5. The imaging device of claim 1 , wherein the data output unit comprises a register outputting encoded image data inputted from the encoding unit by delaying the output by a predetermined clock.

6. The imaging device of claim 1 , wherein the data output unit comprises:

an H_sync generator, generating and outputting a valid data enable signal of high or low state in accordance with a valid data enable control command;

a delay unit, outputting in accordance with a data output control command valid data inputted from the encoding unit as well as invalid data or pre-generated dummy data; and

a transmission control unit, generating and outputting the valid data enable control command and the data output control command.

7. The imaging device of claim 6 , wherein the valid data enable signal is interpreted as a write enable signal in the receiving part.

8. An image signal processor, comprising:

a pre-process unit, executing a pre-process corresponding to any one of filtering and interpolation of an electrical signal corresponding to an external image inputted from an image sensor, and outputting to the image sensor a defer control command for expanding an output section of a vertical synchronous signal corresponding to a (k+1) th frame following a k th frame to be processed after an input of a capture command, k being a natural number;

an encoding unit, generating encoded image data by encoding in accordance with the pre-processed electrical signal; and

a data output unit, outputting the encoded image data to a receiving part,

whereas the image sensor expands the output section of the vertical synchronous signal corresponding to the (k+1) th frame and outputs the vertical synchronous signal in accordance with the defer control command.

9. The image signal processor of claim 8 , wherein an end point of the output section of the vertical synchronous signal outputted from the image sensor coincides with or follows a point at which encoding of the k th frame is completed by the encoding unit, and the end point is either a falling edge or a rising edge.

10. The image signal processor of claim 8 , wherein, once the data output unit detects and notifies to the pre-process unit that encoding of the k th frame is completed, the pre-process unit outputs a return control command to the image sensor,

whereas the return control command resets to a default a length of an output section of a vertical synchronous signal corresponding to a (k+2) th frame, and readjusts a gain value to a default.

11. The image signal processor of claim 8 , wherein the encoded image data outputted for the k th frame is between “START MARKER” and “STOP MARKER”.

12. The image signal processor of claim 8 , wherein the data output unit comprises a register outputting encoded image data inputted from the encoding unit by delaying the output by a predetermined clock.

13. The image signal processor of claim 8 , wherein the data output unit comprises:

an H_sync generator, generating and outputting a valid data enable signal of high or low state in accordance with a valid data enable control command;

a delay unit, outputting in accordance with a data output control command valid data inputted from the encoding unit as well as invalid data or pre-generated dummy data; and

a transmission control unit, generating and outputting the valid data enable control command and the data output control command.

14. The image signal processor of claim 13 , wherein the valid data enable signal is interpreted as a write enable signal in the receiving part.

15. A method of transferring a deferred vertical synchronous signal, the method executed in an image signal processor of an imaging device comprising an image sensor, the method comprising:

being inputted with a capture command;

being inputted with a vertical synchronous signal for a k th frame from an encoding unit, k being a natural number;

transmitting a defer control command for a (k+1) th frame to the image sensor; and

transmitting a return control command to the image sensor if encoding of the k th frame is completed,

whereas the image sensor expands an output section of a vertical synchronous signal corresponding to a (k+1) th frame and outputs the vertical synchronous signal in accordance with the defer control command, and readjusts a length of an output section and a gain value of a vertical synchronous signal corresponding to a (k+2) th frame in accordance with the return control command.

16. The method of claim 15 , wherein an end point of the output section of the vertical synchronous signal outputted from the image sensor coincides with or is outputted following a point at which encoding of the k th frame is completed, and the end point is either a falling edge or a rising edge.

17. The method of claim 15 , wherein completion of encoding the k th frame is determined by using header information and tail information of encoded data.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2025
From: MILA CO., LTD.
To: MILA US INC
Reel/Frame 072980/0728 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 23, 2020
From: MTEKVISION CO., LTD
To: MILA CO., LTD
Reel/Frame 054735/0464 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2008
From: NOH, YO-HWAN
To: MTEKVISION CO., LTD.
Reel/Frame 021010/0333 →
Priority Claims (1)
KR 10-2005-0104607 · Nov 2, 2005 · national
Continuity (1)
Related Publication 20080291509A1 · Nov 27, 2008