Differential amplifier circuit

1. A differential amplifier circuit comprising:

a P-type differential input unit having a non-inverted input end adapted for receiving a first input voltage, and an inverted input end adapted for receiving a second input voltage, said P-type differential input unit outputting a first output in response to the first and second input voltages;

an N-type differential input unit having a non-inverted input end adapted for receiving the first input voltage, and an inverted input end adapted for receiving the second input voltage, said N-type differential input unit outputting a second output in response to the first and second input voltages;

a P-type current mirror circuit coupled to said N-type differential input unit for receiving the second output therefrom, and driven by the second output to generate a first control output;

an N-type current mirror circuit coupled to said P-type differential input unit for receiving the first output therefrom, and driven by the first output to generate a second control output;

an output unit coupled to said P-type and N-type current mirror circuits for receiving the first and second control outputs therefrom, and outputting an output voltage in response to the first and second control outputs from said P-type and N-type current mirror circuits;

a first sub-current source including first and second P-type transistors connected in series, said first P-type transistor having a control end coupled to a common node between said first and second P-type transistors, said second P-type transistor having a control end receiving the first control output from said P-type current mirror circuit such that said second P-type transistor is driven by the first control output from said P-type current mirror circuit; and

a second sub-current source including first and second N-type transistors connected in series, said first N-type transistor having a control end coupled to a common node between said first and second N-type transistors, said second N-type transistor having a control end receiving the second control output from said N-type current mirror circuit such that said second N-type transistor is driven by the second control output from said N-type current mirror circuit.

2. The differential amplifier circuit as claimed in claim 1 , wherein said output unit includes P-type and N-type output transistors connected in series, said P-type output transistor having a control end for receiving the first control output from said P-type current mirror circuit such that said P-type output transistor is driven by the first control output from said P-type current mirror circuit, said N-type output transistors having a control end for receiving the second control output from said N-type current mirror circuit such that said N-type output transistor is driven by the second control output from said N-type current mirror circuit, the output voltage being output at a common node between said P-type and N-type output transistors.

3. The differential amplifier circuit as claimed in claim 1 , further comprising first ands second resistors coupled between said P-type and N-type current mirror circuits.

4. The differential amplifier circuit as claimed in claim 3 , wherein:

said P-type differential input unit includes first, second and third PMOS transistors, a gate of said first PMOS transistor being adapted for receiving a first bias voltage, a drain of said first PMOS transistor being coupled to sources of said second and third PMOS transistors, gates of said second and third PMOS transistors being coupled respectively to said non-inverted and inverted input ends of said P-type differential input unit, the first output being output at drains of said second and third PMOS transistors; and

said N-type differential input unit includes first, second and third NMOS transistors, a gate of said first PMOS transistor being adapted for receiving a second bias voltage, a drain of said first NMOS transistor being coupled to sources of said second and third NMOS transistors, gates of said second and third NMOS transistors being coupled respectively to said non-inverted and inverted input ends of said N-type differential input unit, the second output being output at drains of said second and third NMOS transistors.

5. The differential amplifier circuit as claimed in claim 4 , further comprising first and second capacitors connected in series between said drain of said second NMOS transistor of said N-type differential input unit and said drain of said second PMOS transistor of said P-type differential input unit.

6. The differential amplifier circuit as claimed in claim 4 , wherein:

said first sub-current source is connected in parallel to said first PMOS transistor of said P-type differential input unit; and

said second sub-current source is connected in parallel to said first NMOS transistor of said N-type differential input unit.

7. The differential amplifier circuit as claimed in claim 6 , wherein:

said first sub-current source further includes a first constant current source coupled between said first PMOS transistor of said P-type differential input unit and said first P-type transistor; and

said second sub-current source further includes a second constant current source coupled between said first NMOS transistor of said N-type differential input unit and said first N-type transistor.

8. The differential amplifier circuit as claimed in claim 4 , wherein:

said first sub-current source further includes an N-type sub-current mirror coupled to said second P-type transistor, and a common node among said first, second and third NMOS transistors of said N-type differential input unit; and

said second sub-current source further includes a P-type sub-current mirror coupled to said second N-type transistor, and a common node among said first, second and third PMOS transistors of said P-type differential input unit.

9. The differential amplifier circuit as claimed in claim 8 , wherein:

said first sub-current source further includes a first constant current source coupled between said first PMOS transistor of said P-type differential input unit and said first P-type transistor; and

said second sub-current source further includes a second constant current source coupled between said first NMOS transistor of said N-type differential input unit and said first N-type transistor.

10. The differential amplifier circuit as claimed in claim 8 , wherein:

said N-type sub-current mirror of said first sub-current source includes a first NMOS transistor connected in series to said second P-type transistor, and a second NMOS transistor connected in parallel to said first NMOS transistor of said N-type differential input unit, gates of said first and second NMOS transistors of said N-type sub-current mirror being coupled to a drain of said first NMOS transistor of said N-type sub-current mirror; and

said P-type sub-current mirror of said second sub-current source includes a first PMOS transistor connected in series to said second N-type transistor, and a second PMOS transistor connected in parallel to said first PMOS transistor of said P-type differential input unit, gates of said first and second PMOS transistors of said P-type sub-current mirror being coupled to a drain of said first PMOS transistor of said P-type sub-current mirror.

11. The differential amplifier circuit as claimed in claim 1 , wherein:

each of said first and second P-type transistors of said first sub-current source is a PMOS transistor that has a gate serving as said control end; and

each of said first and second N-type transistors of said second sub-current source is an NMOS transistor that has a gate serving as said control end.