Protection of the execution of a program executed by an integrated circuit

1. A method for protecting the execution of a program by checking the integrity of a calculation executed by an integrated circuit, comprising:

executing, by a processor of the integrated circuit, a program to perform a calculation;

initializing, by the processor of the integrated circuit, at least one counter;

carrying on, by the processor of the integrated circuit, with the program execution during operation of the counter;

interrupting, by the integrated circuit, the program execution when the counter reaches a given value randomly selected from a range of values wherein an upper limit of said range is selected according to the program execution where no instruction prejudicial to data security occurs before the integrity check of the calculation executed; and

executing, by the processor of the integrated circuit, at least one integrity check of the calculation in response to this interrupt.

2. The method of claim 1 , wherein a lower limit of said range is selected to result in a time longer than a time required for the integrity check.

3. The method of claim 1 , wherein said counter is a time counter.

4. The method of claim 1 , wherein said counter is an instruction counter.

5. The method of claim 1 , wherein said counter is a counter of a signal available in the integrated circuit in relation with the calculation time.

6. The method of claim 1 , wherein several integrity checks are performed on intermediary results of the calculation with, each time, initializations of the counter to different values.

7. An integrated circuit comprising at least a central processing unit, a memory, an input/output circuit, and comprising means for implementing the protection method of claim 1 .

8. A smart card, comprising the circuit of claim 7 .

9. A method for protecting the execution of a computer program by an integrated circuit, comprising:

executing, by a processor of the integrated circuit, a program to perform a calculation;

proceeding, by the processor of the integrated circuit, with program execution following completion of the calculation;

interrupting, by the integrated circuit, program execution following completion of the calculation at an interrupt time randomly selected from a range of interrupt times wherein an upper limit of said range is selected to prevent execution of an instruction prejudicial to data security before the integrity check is executed;

executing, by the processor of the integrated circuit, at least one integrity check of the calculation in response to interrupting program execution; and

continuing, by the processor of the integrated circuit, program execution following the integrity check unless the integrity check indicates a lack of integrity.

10. A method as defined in claim 9 , further comprising determining the randomly selected interrupt time with at least one counter.

11. A method as defined in claim 9 , wherein a lower limit of said range is selected to be longer than a time required for the integrity check.

12. A method as defined in claim 9 , further comprising initializing at least one counter, wherein the program execution is interrupted when the counter reaches the randomly selected interrupt time.

13. A method as defined in claim 9 , wherein the acts of interrupting program execution, executing at least one integrity check and continuing program execution are performed two or more times.

14. A method as defined in claim 13 , wherein a different randomly selected interrupt time is used for each interruption of program execution.

15. An integrated circuit comprising:

a memory;

an input/output circuit; and

a central processing unit configured to protect execution of a computer program stored in the memory by:

executing the program to perform a calculation;

proceeding with program execution following completion of the calculation;

interrupting program executing following completion of the calculation at an interrupt time randomly selected from a range of interrupt times wherein an upper limit of said range is selected to prevent execution of an instruction prejudicial from the point of view of data security before the integrity check is executed;

executing at least one integrity check of the calculation in response to interrupting program execution; and

continuing program execution following the integrity check unless the integrity check indicates a lack of integrity.

16. An integrated circuit as defined in claim 15 , wherein the central processing unit is configured to determine the randomly selected interrupt time with at least one counter.

17. An integrated circuit as defined in claim 15 , wherein a lower limit of said range is selected to be longer than the time required for the integrity check.

18. An integrated circuit as defined in claim 15 , wherein the central processing unit is configured to execute two or more integrity checks at different randomly selected interrupt times.