Vertical channel type non-volatile memory device and method for fabricating the same
A method for fabricating a vertical channel type non-volatile memory device including forming a source region, alternately forming a plurality of interlayer dielectric layers and a plurality of conductive layers for a gate electrode over a substrate with the source region formed therein, forming a trench exposing the source region by etching the plurality of interlayer dielectric layers and the plurality of conductive layers for a gate electrode, and siliciding the conductive layers for a gate electrode and the source region that are exposed through the trench.
1. A method for fabricating a vertical channel type non-volatile memory device, comprising:
forming a source region;
alternately forming a plurality of interlayer dielectric layers and a plurality of conductive layers for a gate electrode over a substrate with the source region formed therein;
forming a trench exposing the source region by etching the plurality of interlayer dielectric layers and the plurality of conductive layers for a gate electrode; and
siliciding a portion of the conductive layers for a gate electrode and a portion of the source region that are exposed through the trench.
2. The method of claim 1 , further comprising:
forming a channel trench by etching the plurality of the interlayer dielectric layers and the plurality of the conductive layers for a gate electrode;
sequentially forming a charge blocking layer, a charge trapping layer or a charge storage layer, and a tunnel insulation layer on an internal wall of the channel trench; and
forming a channel by filling the channel trench with a layer for a channel.
3. The method of claim 1 , wherein the forming of the trench exposing the source region,
a plurality of memory blocks are separated from each other by etching the plurality of the interlayer dielectric layers and the plurality of the conductive layers for a gate electrode.
4. The method of claim 1 , wherein the siliciding of the conductive layers for a gate electrode and the source region that are exposed through the trench includes:
filling the trench with a metal layer;
reacting the conductive layers for a gate electrode, the source region, and the metal layer through a thermal treatment; and
removing the metal layer that remains unreacted after the thermal treatment.
5. The method of claim 4 , further comprising:
filling the trench with an insulation layer, after the siliciding of the conductive layers for a gate electrode and the source region;
forming a second trench exposing the silicided source region by etching the insulation layer; and
forming a contact plug by filling the second trench with a conductive layer.
6. The method of claim 1 , wherein the alternately forming of the plurality of the interlayer dielectric layers and the plurality of the conductive layers for a gate electrode over the substrate with the source region formed therein comprises:
alternately forming the plurality of the interlayer dielectric layers and a plurality of sacrificial layers over the substrate;
forming a channel trench by etching the plurality of the interlayer dielectric layers and the plurality of the sacrificial layers;
forming a channel by filling the channel trench with a layer for a channel;
exposing sidewalls of the channel by removing the plurality of the sacrificial layers; and
filling the exposed sidewalls with a conductive layer for a gate electrode.
7. The method of claim 6 , further comprising:
sequentially forming a tunnel insulation layer, a charge trapping layer or a charge storage layer, and a charge blocking layer on the internal sidewalls of the channel trench, before forming the channel.
8. The method of claim 1 , further comprising:
forming a channel trench by etching the plurality of the interlayer dielectric layers and the plurality of the conductive layers for a gate electrode;
forming a gate insulation layer on an internal wall of the channel trench; and
forming a channel by filling the channel trench with a layer for a channel.