Photomask design verification

1. A method of verifying a photomask design performed using at least one computing device, the method comprising:

simulating an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconductor manufacturing process, to generate a plurality of contours for the initial semiconductor manufacturing process, using the at least one computing device;

simulating a subsequent semiconductor manufacturing process using the contours for the initial semiconductor manufacturing process and variation models for the subsequent semiconductor manufacturing process, to generate a plurality of contours for the subsequent semiconductor manufacturing process, using the at least one computing device;

repeatedly simulating at least one further subsequent semiconductor manufacturing process using a plurality of contours for the subsequent semiconductor manufacturing process and variation models for the further subsequent semiconductor manufacturing process; and

generating and storing a verification result for the photomask design on a computer readable storage medium.

2. The method of claim 1 , further comprising:

generating a target for the initial semiconductor manufacturing process.

3. The method of claim 2 , further comprising:

identifying a difference between the target for the initial semiconductor manufacturing process and the plurality of contours for the initial semiconductor manufacturing process in a case that a difference exists.

4. The method of claim 3 , further comprising:

comparing the difference to a predetermined set of failure limits for the initial semiconductor manufacturing process; and

wherein the generating and storing a verification result includes logging an error in an error log in a case that the difference is outside of the predetermined set of failure limits.

5. The method of claim 4 , further comprising:

determining whether a final semiconductor manufacturing process has been simulated in a case that the difference is within the predetermined set of failure limits.

6. The method of claim 5 , further comprising initiating the simulating of the subsequent semiconductor manufacturing process in response to the determining that the final semiconductor manufacturing process has not been simulated.

7. The method of claim 1 , further comprising:

generating a target for the subsequent semiconductor manufacturing process;

measuring a difference between the target for the subsequent semiconductor manufacturing process and the plurality of contours for the subsequent semiconductor manufacturing process in a case that a difference exists;

comparing the difference to a predetermined set of failure limits for the subsequent semiconductor manufacturing process;

logging an error in an error log in a case that the difference is outside of the predetermined set of failure limits and the error is not fixable;

creating a new target for a preceding semiconductor manufacturing process in a case that the error is fixable; and

repeating the simulating of the initial semiconductor manufacturing process using the new target and the variation models for the initial semiconductor manufacturing process, to generate a plurality of new contours for the initial semiconductor manufacturing process.

8. A system for verifying a photomask design, the system comprising:

a computer-implemented simulator for:

simulating an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconductor manufacturing process, to generate a plurality of contours for the initial semiconductor manufacturing process;

simulating a subsequent semiconductor manufacturing process using the contours for the initial semiconductor manufacturing process and variation models for the subsequent semiconductor manufacturing process, to generate a plurality of contours for the subsequent semiconductor manufacturing process; and

repeatedly simulating at least one further subsequent semiconductor manufacturing process using a plurality of contours for the subsequent semiconductor manufacturing process and variation models for the further subsequent semiconductor manufacturing process.

9. The system of claim 8 , further comprising:

a mask data preparer for generating a target for the initial semiconductor manufacturing process.

10. The system of claim 9 , further comprising:

an identifier for identifying a difference between the target for the initial semiconductor manufacturing process and the plurality of contours for the initial semiconductor manufacturing process in a case that a difference exists.

11. The system of claim 10 , further comprising:

a comparator for:

comparing the difference to a predetermined set of failure limits for the initial semiconductor manufacturing process; and

logging an error in an error log in a case that the difference is outside of the predetermined set of failure limits.

12. The system of claim 11 , wherein the comparator further performs the following:

determines whether a final semiconductor manufacturing process has been simulated in a case that the difference is within the predetermined set of failure limits.

13. The system of claim 12 , wherein the comparator further performs the following:

initiates the simulating of the subsequent semiconductor manufacturing process in response to the determining that the final semiconductor manufacturing process has not been simulated.

14. The system of claim 8 , further comprising:

a mask data preparer for generating a target for the subsequent semiconductor manufacturing process;

an identifier for identifying a difference between the target for the subsequent semiconductor manufacturing process and the plurality of contours for the subsequent semiconductor manufacturing process in a case that a difference exists;

a comparator for:

comparing the difference to a predetermined set of failure limits for the subsequent semiconductor manufacturing process; and

logging an error in an error log in a case that the difference is outside of the predetermined set of failure limits and the error is not fixable; and

a corrector for creating a new target for a preceding semiconductor manufacturing process in a case that the error is fixable;

wherein the simulator repeats the simulating of the initial semiconductor manufacturing process using the new target and the variation models for the initial semiconductor manufacturing process, to generate a plurality of new contours for the initial semiconductor manufacturing process.

15. A computer program product stored on a computer readable storage medium, which when executed by a computer, performs the following:

simulates an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconductor manufacturing process, to generate a plurality of contours for the initial semiconductor manufacturing process;

simulates a subsequent semiconductor manufacturing process using the contours for the initial semiconductor manufacturing process and variation models for the subsequent semiconductor manufacturing process, to generate a plurality of contours for the subsequent semiconductor manufacturing process; and

repeatedly simulates at least one further subsequent semiconductor manufacturing process using a plurality of contours for the subsequent semiconductor manufacturing process and variation models for the further subsequent semiconductor manufacturing process.

16. The computer program product of claim 15 , which further performs the following:

generates a target for the initial semiconductor manufacturing process.

17. The computer program product of claim 16 , which further performs the following:

identifies a difference between the target for the initial semiconductor manufacturing process and the plurality of contours for the initial semiconductor manufacturing process in a case that a difference exists.

18. The computer program product of claim 17 , which further performs the following:

compares the difference to a predetermined set of failure limits for the first semiconductor manufacturing process; and

logs an error in an error log in a case that the difference is outside of the predetermined set of failure limits.

19. The computer program product of claim 18 , which further performs the following:

determines whether a final semiconductor manufacturing process has been simulated in a case that the difference is within the predetermined set of failure limits.

20. The computer program product of claim 15 , which further performs the following:

generates a target for the subsequent semiconductor manufacturing process;

measures a difference between the target for the subsequent semiconductor manufacturing process and the plurality of contours for the subsequent semiconductor manufacturing process in a case that a difference exists;

compares the difference to a predetermined set of failure limits for the subsequent semiconductor manufacturing process;

logs an error in an error log in a case that the difference is outside of the predetermined set of failure limits and the error is not fixable;

creates a new target for a preceding semiconductor manufacturing process in a case that the error is fixable; and

repeats the simulating of the initial semiconductor manufacturing process using the new target and the variation models for the initial semiconductor manufacturing process, to generate a plurality of new contours for the initial semiconductor manufacturing process.