IP Library Granted Patent US 8,169,048
Granted Patent B2
US 8,169,048 · App. 13/023,992 · Granted May 1, 2012

Isolation structure in a memory device

Assignee: Hynix Semiconductor Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,169,048
App. No.
13/023,992
Granted
May 1, 2012
Kind
B2
Abstract

An isolation structure in a memory device and a method for fabricating the isolation structure. In the method, a first trench is formed in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. A liner layer comprising a silicon nitride layer is formed on the first and second trenches. A spin on dielectric (SOD) layer comprising polysilazane is formed on the liner layer so as to fill the first and second trenches. A portion of the SOD layer filling the second trench is removed. A portion of the silicon nitride layer, which is disposed on the second trench and is exposed after the removing of the portion of the SOD layer, is oxidized using oxygen plasma and heat generated from the plasma. A high density plasma (HDP) oxide layer is formed to fill the second trench.

Claims (6)

1. An isolation structure in a memory device, comprising:

a semiconductor substrate comprising a first trench in a cell region and a second trench in a peripheral region, the first trench defining a first active region of the semiconductor substrate in which a channel of an n-channel metal oxide semiconductor (NMOS) transistor is to be formed, the second trench being wider than the first trench and defining a second active region of the semiconductor substrate in which a channel of a p-channel metal oxide semiconductor (PMOS) transistor is to be formed;

a first liner layer disposed on the first trench and comprising a wall oxide layer portion formed by oxidizing a surface of the first trench and a silicon nitride layer portion disposed on the wall oxide layer portion and a first silicon oxide layer disposed on the silicon nitride layer;

a flowable dielectric layer comprising a polysilazane spin on dielectric (SOD) layer, disposed directly on the first silicon oxide layer of the first liner layer to fill the first trench;

a second liner layer disposed on the second trench and comprising the wall oxide layer portion formed by oxidizing a surface of the second trench and a second oxide layer formed by oxidizing the silicon nitride layer portion disposed on the wall oxide layer portion by using oxygen plasma; and

a high density plasma (HDP) oxide layer disposed directly on the second oxide layer of the second liner layer to fill the second trench.

Priority Claims (1)
KR 10-2008-0033168 · Apr 10, 2008 · national
Continuity (2)
Division 12164579 · Jun 30, 2008
Related Publication 20110127634A1 · Jun 2, 2011