Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device, comprising:

a plurality of first memory strings each having a plurality of electrically rewritable first memory transistors connected in series;

a first select transistor having one end thereof connected to one end of the first memory string;

a first line commonly connected to the other end of a plurality of the first select transistors;

a switch circuit having one end thereof connected to the first line; and

a second line commonly connected to the other end of a plurality of the switch circuits,

the first memory string comprising:

a first semiconductor layer including a first columnar portion that extends in a perpendicular direction to a substrate and functioning as a body of the first memory transistors;

a first charge storage layer formed surrounding a side surface of the first columnar portion; and

a first conductive layer formed surrounding the first charge storage layer and functioning as a gate of the first memory transistors,

the switch circuit controlling electrical connection between the second line and the first line.

2. The nonvolatile semiconductor memory device according to claim 1 ,

wherein the switch circuit comprises a transistor formed on the substrate.

3. The nonvolatile semiconductor memory device according to claim 2 ,

wherein the first semiconductor layer comprises a joining portion configured to join ends in the perpendicular direction of a pair of the columnar portions, and

wherein the first memory string further comprises:

a second conductive layer formed surrounding a side surface of the joining portion with the first charge storage layer interposed therebetween.

4. The nonvolatile semiconductor memory device according to claim 3 ,

wherein the transistor comprises a third conductive layer functioning as a gate of the transistor, and

wherein the third conductive layer is formed in the same layer as the second conductive layer.

5. The nonvolatile semiconductor memory device according to claim 3 ,

wherein the transistor comprises a third conductive layer functioning as a gate of the transistor, and

wherein the third conductive layer is formed in a layer downward of the second conductive layer.

6. The nonvolatile semiconductor memory device according to claim 1 ,

wherein the switch circuit comprises at least a second select transistor having an identical structure to the first select transistor, and

wherein the first line and the second line are connected to each other through conduction of the second select transistor.

7. The nonvolatile semiconductor memory device according to claim 1 ,

wherein the switch circuit comprises at least a second memory string having an identical structure to the first memory string, and

wherein the first line and the second line are connected to each other through conduction of the second memory string.

8. The nonvolatile semiconductor memory device according to claim 6 ,

wherein the switch circuit comprises:

a second semiconductor layer including a second columnar portion extending in the perpendicular direction to the substrate and having an elliptical shape cross section in a horizontal direction, a length of the elliptical shape in a long axis direction being set to such a length as to contain therein a plurality of the first semiconductor layers;

a third semiconductor layer including a third columnar portion extending in the perpendicular direction to the substrate from an end of an upper surface of the second semiconductor layer and having a width in the long axis direction less than that of the second semiconductor layer, and functioning as a body of the second select transistor;

a second conductive layer provided in a periphery of the second semiconductor layer with an insulating film interposed therebetween, and provided in the same layer as the first conductive layer; and

a third conductive layer provided in a periphery of the third semiconductor layer with an insulating film interposed therebetween, and functioning as a control electrode of the second select transistor.

9. The nonvolatile semiconductor memory device according to claim 8 ,

wherein at least two or more third semiconductor layers are provided on an upper surface of one of the second semiconductor layer.

10. The nonvolatile semiconductor memory device according to claim 8 ,

wherein the first conductive layer has a width in a first direction parallel to the substrate and extends in a second direction parallel to the substrate and orthogonal to the first direction, and

wherein the first conductive layer provided next to the second conductive layer has a width less than other ones of the first conductive layers.

11. The nonvolatile semiconductor memory device according to claim 8 ,

wherein the first conductive layer has a width in a first direction parallel to the substrate and extends in a second direction parallel to the substrate and orthogonal to the first direction, and

wherein the first conductive layer provided next to the second conductive layer has the same width as other ones of the first conductive layers.

12. The nonvolatile semiconductor memory device according to claim 8 , further comprising:

a first dummy semiconductor layer provided with a certain periodic pattern in a direction parallel to the substrate together with the first columnar portion and extending in the perpendicular direction to the substrate,

wherein the first conductive layer provided next to the second conductive layer is formed to surround the first semiconductor layer and the first dummy semiconductor layer.

13. The nonvolatile semiconductor memory device according to claim 8 , further comprising:

a second dummy semiconductor layer provided with a certain periodic pattern in a direction parallel to the substrate together with the first columnar portion and extending in the perpendicular direction to the substrate,

wherein the second conductive layer is formed to surround the second semiconductor layer and the second dummy semiconductor layer.

14. The nonvolatile semiconductor memory device according to claim 8 ,

wherein the second conductive layer comprises a trench provided with a certain pitch along a longer direction of the second conductive layer, a periphery of the trench being silicided.

15. The nonvolatile semiconductor memory device according to claim 1 , wherein a plurality of the first memory transistors are disposed in a plurality of first blocks, further comprising:

a plurality of third lines provided for each of the first blocks and each commonly connected to gates of the plurality of first memory transistors;

a plurality of first transfer circuits each connected to a respective one of the third lines; and

a fourth line commonly connected to the plurality of first transfer circuits,

wherein each of the first transfer circuits is supplied with a first drive signal and transfers the first drive signal to the respective one of the third lines based on a first control signal supplied from the fourth line.

16. The nonvolatile semiconductor memory device according to claim 1 , wherein a plurality of the first memory transistors are disposed in a plurality of first blocks, further comprising:

a plurality of third lines provided for each of the first blocks and each commonly connected to gates of the plurality of first memory transistors;

a fourth line commonly connected to the plurality of third lines; and

a first transfer circuit connected to the fourth line,

wherein the first transfer circuit is supplied with a first drive signal and selectively transfers the first drive signal to the third lines via the fourth line.

17. The nonvolatile semiconductor memory device according to claim 15 ,

wherein the third lines are constituted by polysilicon and the fourth line is constituted by a metal.

18. The nonvolatile semiconductor memory device according to claim 1 , wherein the switch circuit comprises a plurality of second memory transistors having an identical structure to that of the first memory transistors and disposed in a plurality of second blocks, further comprising:

a plurality of fifth lines provided to each of the second blocks and each commonly connected to gates of the plurality of second memory transistors;

a plurality of second transfer circuits each connected to a respective one of the fifth lines; and

a sixth line commonly connected to the plurality of second transfer circuits,

wherein each of the second transfer circuits is supplied with a second drive signal and transfers the second drive signal to the respective one of the fifth lines based on a second control signal supplied from the sixth line.

19. The nonvolatile semiconductor memory device according to claim 1 , wherein the switch circuit comprises a plurality of second memory transistors having an identical structure to that of the first memory transistors and disposed in a plurality of second blocks, further comprising:

a plurality of fifth lines provided to each of the second blocks and each commonly connected to gates of the plurality of second memory transistors;

a sixth line commonly connected to the plurality of fifth lines; and

a second transfer circuit connected to the sixth line,

wherein the second transfer circuit is supplied with a second drive signal and selectively transfers the second drive signal to the fifth lines via the sixth line.

20. The nonvolatile semiconductor memory device according to claim 18 ,

wherein the fifth lines are constituted by polysilicon and the sixth line is constituted by a metal.