IP Library Granted Patent US 8,173,514
Granted Patent B2
US 8,173,514 · App. 12/369,859 · Granted May 8, 2012

Method of manufacturing semiconductor device

Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 8,173,514
App. No.
12/369,859
Granted
May 8, 2012
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.

Claims (32)

1. A method of manufacturing a semiconductor device, comprising:

forming an isolation region defining an active region in a semiconductor substrate;

forming a silicon oxide film in the isolation region and polishing an upper portion of the silicon oxide film formed in the isolation region;

forming a sacrifice oxide film over the active region;

forming wells in the active region;

removing the sacrifice oxide film, a recess being formed in the isolation region adjacent to the boundary between the active region and the isolation region as a result of the removal of the sacrifice oxide film;

after removing the sacrifice oxide film, forming a first insulating film over the semiconductor substrate;

forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film;

selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas to form a fluorocarbon film over the first insulating film;

removing the fluorocarbon film by exposing to a mixed gas including an Ar gas and oxygen gas in a magnetron RIE apparatus; and

selectively removing the first insulating film from the first region by wet etching.

2. The method according to claim 1 , wherein the removing the fluorocarbon film is performed by using the oxygen gas having a flow rate of 0.5% to 25% of the total flow rate of the mixed gas.

3. The method according to claim 1 , wherein the selectively removing the second insulating film and the removing the fluorocarbon film are continuously performed in the same process chamber.

4. The method according to claim 1 , wherein the third insulating film is formed to have etching properties equivalent to those of the first insulating film.

5. The method according to claim 1 , further comprising

forming an MIS transistor having a gate insulating film and a gate electrode in the active region within the first region,

wherein the gate insulating film is formed on the active region of the first region after the selectively removing the first insulating film, and the gate electrode is formed on the gate insulating film.

6. The method according to claim 5 , wherein the forming the gate electrode is performed by forming the gate electrode including at least a fourth insulating film formed by thermal oxidation of the semiconductor substrate exposed by the selectively removing the first insulating film.

7. The method according to claim 1 , further comprising

forming a nonvolatile memory having the first insulating film and the second insulating film over the active region of a second region different from the first region.

8. The method according to claim 7 , wherein the forming the non-volatile memory having the first insulating film and the second insulating film over the active region of the second region different from the first region includes

forming a tunnel gate insulating film over the active region of the second region,

forming a floating gate having the first insulating film and the second insulating film over the tunnel gate insulating film in the second region after the forming the isolation region and before the forming the first insulating film, and

forming a control gate above the floating gate after the selectively removing the first insulating film from the first region.

9. The method according to claim 7 , wherein the forming the non-volatile memory having the first insulating film and the second insulating film over the active region of the second region different from the first region includes

selectively removing the first insulating film over the second region after the forming the first insulating film over the semiconductor substrate,

forming the second insulating film over the active region of the second region, the second insulating film being able to accumulate a charge, and

forming a control gate over the second insulating film.

10. The method according to claim 1 , wherein the forming the isolation region is performed by embedding the insulating film in a trench formed in the semiconductor substrate.

11. The method according to claim 1 , wherein the first insulating film includes silicon oxide.

12. The method according to claim 1 , wherein the second insulating film includes silicon nitride.

13. The method according to claim 1 , wherein the second insulating film includes silicon nitride and silicon oxide.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2009
From: OGURA, JUSUKE; KOKURA, HIKARU; KOJIMA, HIDEYUKI; ANEZAKI, TORU; OGAWA, HIROYUKI; ARIYOSHI, JUNICHI
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 022249/0906 →
Priority Claims (1)
JP 2008-041782 · Feb 22, 2008 · national
Continuity (1)
Related Publication 20090215243A1 · Aug 27, 2009