Method of operating nonvolatile memory device
A method of operating a nonvolatile memory device, including a memory cell array, which further includes a drain select transistor, a memory cell string, and a source select transistor coupled between a bit line and a source line, where the method includes precharging the bit line, setting the memory cell string in a ground voltage state, coupling the memory cell string and the bit line together and supplying a read voltage or a verification voltage to a selected memory cell of the memory cell string, and coupling the memory cell string and the source line together in order to change a voltage level of the bit line in response to a threshold voltage of the selected memory cell.
1. A method of operating a nonvolatile memory device, including a memory cell array, which includes a drain select transistor, a memory cell string, and a source select transistor coupled between a bit line and a source line, the method comprising:
precharging the bit line;
setting the memory cell string in a ground voltage state;
coupling the memory cell string and the bit line together and supplying a read voltage or a verification voltage to a selected memory cell of the memory cell string; and
coupling the memory cell string and the source line together in order to change a voltage level of the bit line in response to a threshold voltage of the selected memory cell.
2. The method of claim 1 , wherein setting the memory cell string in a ground voltage state comprises discharging channel regions of memory cells included in the memory cell string.
3. The method of claim 2 , wherein discharging channel regions of the memory cells included in the memory cell string comprises:
supplying a pass voltage to all of the memory cells; and
coupling the channel regions and the source line together.
4. The method of claim 2 , wherein discharging channel regions of the memory cells included in the memory cell string comprises:
supplying a ground voltage to the source line; and
turning on the source select transistor.
5. The method of claim 1 , wherein:
the bit line is maintained in a precharge state by a page buffer until the memory cell string is coupled to the source line, and
the bit line and the page buffer are disconnected from each other when the memory cell string is coupled to the source line.
6. The method of claim 1 , wherein supplying the read voltage or the verification voltage to the selected memory cell of the memory cell string comprises:
supplying a ground voltage to the selected memory cell; and
supplying the read voltage or the verification voltage to a word line corresponding to the selected memory cell.
7. The method of claim 3 , wherein the read voltage or the verification voltage is less than the pass voltage.
8. The method of claim 1 , wherein precharging the bit line comprises:
precharging a sense node to a high voltage level; and
coupling the sense node and the bit line together by supplying a bit line selection signal to a bit line selection unit.
9. The method of claim 1 , wherein precharging the bit line comprises:
precharging a sense node to a high voltage level; and
coupling the sense node and the bit line together by supplying a bit line sense signal to a bit line sense unit.
10. The method of claim 1 , wherein coupling the memory cell string and the bit line together and supplying the read voltage or the verification voltage to the selected memory cell of the memory cell string comprises:
turning on the drain select transistor; and
supplying the read voltage or the verification voltage to a word line corresponding to the selected memory cell.
11. The method of claim 1 , further comprising:
after coupling the memory cell string and the source line together,
disconnecting the bit line and a sense node from each other, and discharging the memory cell string, and, at the same time, evaluating the voltage level of the bit line in response to the threshold voltage of the selected memory cell; and
coupling the bit line and the sense node, which is in a floating state, and sensing a voltage level of the sense node in response to the evaluated voltage level of the bit line.
12. A method of operating a nonvolatile memory device, including a memory cell array, which includes a drain select transistor, a memory cell string, and a source select transistor coupled between a bit line and a source line, the method comprising:
precharging the bit line and supplying a ground voltage to the source line;
turning on memory cells, included in the memory cell string, and the source select transistor;
turning off the source select transistor, supplying a verification voltage or a read voltage to a selected memory cell from among the memory cells, and turning on the drain select transistor; and
turning on the source select transistor in order to change a voltage level of the bit line in response to a threshold voltage of the selected memory cell.
13. The method of claim 12 , wherein:
the bit line is maintained in a precharge state by a page buffer until the turning on of the source select transistor in order to change the voltage level of the bit line in response to the threshold voltage of the selected memory cell, and
the bit line and the page buffer are disconnected from each other at the same time as the turning on of the source select transistor in order to change the voltage level of the bit line in response to the threshold voltage of the selected memory cell.
14. The method of claim 12 , wherein turning on the memory cells, included in the memory cell string, and the source select transistor comprises:
supplying a pass voltage to all of the memory cells included in the memory cell string; and
turning on the source select transistor.
15. The method of claim 12 , wherein supplying the verification voltage or the read voltage to the selected memory cell from among the memory cells comprises:
supplying the ground voltage to the selected memory cell; and
supplying the read voltage or the verification voltage to a word line corresponding to the selected memory cell.
16. The method of claim 14 , wherein the read voltage or the verification voltage is less than the pass voltage.
17. The method of claim 12 , wherein precharging the bit line and supplying the ground voltage to the source line comprises:
precharging a sense node to a high voltage level;
coupling the sense node and the bit line together by supplying a bit line selection signal to a bit line selection unit; and
supplying the ground voltage to the source line.
18. The method of claim 12 , wherein precharging the bit line and supplying the ground voltage to the source line comprises:
precharging a sense node to a high voltage level;
coupling the sense node and the bit line together by supplying a bit line sense signal to a bit line sense unit; and
supplying the ground voltage to the source line.
19. The method of claim 12 , further comprising:
after turning on the source select transistor in order to change the voltage level of the bit line in response to the threshold voltage of the selected memory cell,
disconnecting the bit line and a sense node from each other, and discharging the memory cell string, and, at the same time, evaluating the voltage level of the bit line in response to the threshold voltage of the selected memory cell; and
coupling the bit line and the sense node, which is in a floating state, and sensing a voltage level of the sense node in response to the evaluated voltage level of the bit line.