Apparatus for detecting jitter of phase locked loop
A method and apparatus for detecting jitter of a Phase Locked Loop (PLL), which is capable of detecting a jitter level of the PLL without using a separate jitter measurement device, is disclosed. The apparatus for detecting the jitter of the PLL includes the PLL configured to detect a phase difference signal between a reference clock and a feedback clock and to generate an oscillation signal having a predetermined frequency according to the phase difference signal, a variable phase delay unit configured to switch a plurality of capacitors according to an input delay control signal and to delay the phase difference signal from the PLL according to the delay control signal, a comparator configured to compare the phase difference signal from the PLL with the phase difference signal delayed by the variable phase delay unit and to detect a delay period of the phase difference signal, and a lock detection unit configured to detect whether the oscillation signal is within a lock range after the delay period detected by the comparator.
1. An apparatus for detecting jitter of a Phase Locked Loop (PLL), the apparatus comprising:
the PLL configured to detect a phase difference signal between a reference clock and a feedback clock and to generate an oscillation signal having a predetermined frequency according to the phase difference signal;
a variable phase delay unit configured to switch a plurality of capacitors according to an input delay control signal and to delay the phase difference signal from the PLL according to the delay control signal;
a comparator configured to compare the phase difference signal from the PLL with the phase difference signal delayed by the variable phase delay unit and to detect a delay period of the phase difference signal; and
a lock detection unit configured to detect whether the oscillation signal is within a lock range after the delay period detected by the comparator.
2. The apparatus according to claim 1 , wherein the variable phase delay unit includes:
a plurality of inverter buffers connected to an input/output line in series;
a plurality of capacitors connected to a connection line of the plurality of inverter buffers in parallel; and
a plurality of switches configured to switch the plurality of capacitors in response to bits of the delay control signal.
3. The apparatus according to claim 1 , wherein whether the phase difference signal delayed by the delay control signal is within the lock range is detected.
4. A method for detecting jitter of a Phase Locked Loop (PLL), the method comprising:
detecting a phase difference signal between a reference clock and a feedback clock so as to generate an oscillation signal having a predetermined frequency according to the phase difference signal;
switching a plurality of capacitors according to an input delay control signal so as to delay the phase difference signal according to the delay control signal;
comparing the phase difference signal and the delayed phase difference signal so as to detect a delay period of the phase difference signal; and
generating a lock detection signal indicating whether the oscillation signal is within a lock range after the detected delay period.
5. The method according to claim 4 , wherein the plurality of capacitors is switched in response to bits of the delay control signal so as to determine the delay period of the phase difference signal.
6. The method according to claim 4 , wherein whether the phase difference signal delayed by the delay control signal is within the lock range is detected.