Single event upset hardened static random access memory cell
View Patent ↗A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first transistor, a second transistor and a first resistor connected between a source of the first transistor and a drain of the second transistor. The SEU hardened memory cell also includes a third transistor, a fourth transistor and a second resistor connected between a source of the third transistor and a drain of the fourth transistor. The first resistor is also connected between a gate of the third transistor and the drain of the second transistor. The second resistor is also connected between a gate of the first transistor and the drain of the fourth transistor.
1. A single event upset hardened memory cell comprising:
a first resistor and a second resistor;
a first transistor and a second transistor, wherein said first resistor is connected between a source of said first transistor and a drain of said second transistor, wherein said second resistor is connected between a gate of said first transistor and a gate of said second transistor;
a third transistor and a fourth transistor, wherein said second resistor is connected between a source of said third transistor and a drain of said fourth transistor, wherein said first resistor is connected between a gate of said third transistor and a gate of said fourth transistor; and
a capacitor connected between said drain of said second transistor and said drain of said fourth transistor.
2. The memory cell of claim 1 , wherein said second transistor is an n-channel transistor and said first transistor is a p-channel transistor, and said fourth transistor is an n-channel transistor and said third transistor is a p-channel transistor.
3. The memory cell of claim 1 , wherein said capacitor is a metal-insulator-metal capacitor.
4. The memory cell of claim 3 , wherein said metal-insulator-metal capacitor is physically located on top of said first, second, third and fourth transistors.
5. The memory cell of claim 1 , wherein said memory cell further includes a second capacitor connected between said drain of said second transistor and ground.
6. The memory cell of claim 1 , wherein said memory cell further includes a third capacitor connected between said drain of said fourth transistor and ground.
7. A memory device, comprising:
a sense amplifier;
an addressing circuitry having a row decoder and a column decoder;
an array of wordlines and complementary bit line pairs, coupled to said sense amplifier and said addressing circuitry;
a plurality of memory cells located at an intersection of each of said wordlines and said bitline pairs, wherein each of said plurality of memory cells has a single event upset hardened bi-stable circuit that includes:
a first resistor and a second resistor;
a first transistor and a second transistor, wherein said first resistor is connected between a source of said first transistor and a drain of said second transistor, wherein said second resistor is connected between a gate of said first transistor and a gate of said second transistor;
a third transistor and a fourth transistor, wherein said second resistor is connected between a source of said third transistor and a drain of said fourth transistor, wherein said first resistor is connected between a gate of said third transistor and a gate of said fourth transistor: and
a capacitor connected between said drain of said second transistor and said drain of said fourth transistor.
8. The memory device of claim 7 , wherein said second transistor is an n-channel transistor and said first transistor is a p-channel transistor, and said fourth transistor is an n-channel transistor and said third transistor is a p-channel transistor.
9. The memory device of claim 7 , wherein said capacitor is a metal-insulator-metal capacitor.
10. The memory device of claim 9 , wherein said metal-insulator-metal capacitor is physically located on top of said first, second, third and fourth transistors.
11. The memory device of claim 7 , wherein said memory cell further includes a second capacitor connected between said drain of said second transistor and ground.
12. The memory device of claim 7 , wherein said memory cell further includes a third capacitor connected between said drain of said fourth transistor and ground.
13. An apparatus, comprising:
an electronic system; and
a memory device having a plurality of memory cells, wherein each of said plurality of memory cells has a single event upset hardened bi-stable circuit that includes:
a first resistor and a second resistor;
a first transistor and a second transistor, wherein said first resistor is connected between a source of said first transistor and a drain of said second transistor, wherein said second resistor is connected between a gate of said first transistor and a gate of said second transistor;
a third transistor and a fourth transistor, wherein said second resistor is connected between a source of said third transistor and a drain of said fourth transistor, wherein said first resistor is connected between a gate of said third transistor and a gate of said fourth transistor; and
a capacitor connected between said drain of said second transistor and said drain of said fourth transistor.
14. The apparatus of claim 13 , wherein said second transistor is an n-channel transistor and said first transistor is a p-channel transistor, and said fourth transistor is an n-channel transistor and said third transistor is a p-channel transistor.
15. The apparatus of claim 13 , wherein said capacitor is a metal-insulator-metal capacitor.
16. The apparatus of claim 15 , wherein said metal-insulator-metal capacitor is physically located on top of said first, second, third and fourth transistors.
17. The apparatus of claim 13 , wherein said memory cell further includes a second capacitor connected between said drain of said second transistor and ground, and a third capacitor connected between said drain of said fourth transistor and ground.