Ferroelectric memory device for adjusting the capacitor of a bit line
By separately setting a capacitor on BL depending on whether the mode is a DRAM mode or an FRAM mode, it is compatible with improvement in a speed by BL capacitor reduction in the DRAM mode and a sufficient BL capacitance in the FRAM mode. A ferroelectric memory device includes: a plurality of bit lines BL disposed in a column direction; a plurality of word lines WL disposed in a row direction; a plurality of plate lines PL and a bit line capacitor control signal BLC; a ferroelectric memory cell ( 32 ) disposed at an intersection of the plurality of bit lines BL, the plurality of word lines WL, and the plurality of plate lines PL, and composed of a ferroelectric capacitor CF and a memory cell transistor QM; and a load capacitor adjustment cell ( 34 ) disposed at an intersection of the plurality of bit lines BL and the bit line capacitor control signal BLC, and composed of a load capacitor CL and a load capacitor adjustment transistor QL.
1. A ferroelectric memory device comprising:
a plurality of bit lines disposed in a column direction;
a plurality of word lines intersecting perpendicularly with the bit lines and disposed in a row direction;
a plurality of plate lines intersecting perpendicularly with the bit lines and disposed in a row direction;
a bit line control line intersecting perpendicularly with the bit line and disposed in a row direction;
a ferroelectric memory cell disposed adjacent an intersection of one of the bit lines and one of the word lines, and adjacent an intersection of the bit line and one of the plate lines, the ferroelectric memory cell including a ferroelectric capacitor and a memory cell transistor, an electrode of one side of the ferroelectric capacitor being connected to the plate line, the memory cell transistor connecting a source to an electrode of another side of the ferroelectric capacitor, connecting a drain to the bit line, and connecting a gate to the word line; and
a load capacitor adjustment cell disposed adjacent an intersection of one of the bit lines and the bit line control line, the load capacitor adjustment cell including a load capacitor and a load capacitor adjustment transistor, an electrode of one side of the load capacitor being connected to ground potential, the load capacitor adjustment transistor connecting a source to an electrode of another side of the load capacitor, connecting a drain to the bit line, and connecting a gate to the bit line control line,
wherein both of the ferroelectric memory cell and the load capacitor adjustment cell are commonly connected to a same one of the bit lines.
2. The ferroelectric memory device according to claim 1 , wherein the ferroelectric capacitor comprises at least one ferroelectric thin film layer.
3. The ferroelectric memory device according to claim 2 , wherein data stored in the ferroelectric memory cell is held by one of an electric charge charged by the ferroelectric capacitor and a quantity of residual polarization electric charge inside the ferroelectric thin film layer.
4. The ferroelectric memory device according to claim 1 , wherein a capacitor of the bit line connected to the ferroelectric memory cell is adjusted.
5. The ferroelectric memory device according to claim 3 , wherein when reading the data in the ferroelectric memory cell, the load capacitor adjustment cell switches the capacitor of the bit line depending on the case of being held with the quantity of electrically charged up charged by the ferroelectric capacitor, and the case of being held by the quantity of residual polarization electric charge inside the ferroelectric thin film layer.
6. The ferroelectric memory device according to claim 5 , wherein when held with the quantity of electrically charged up charged by the ferroelectric capacitor, data is held also as the quantity of residual polarization electric charge inside the ferroelectric thin film layer at the time of a refresh operation.
7. The ferroelectric memory device according to claim 5 , wherein after power supply cutoff, data is held for the memory cell which does not hold data as the quantity of residual polarization electric charge inside the ferroelectric thin film layer, as the quantity of residual polarization electric charge inside the ferroelectric thin film layer.
8. The ferroelectric memory device according to claim 5 , wherein after powering ON, data is held for the memory cell which holds data as the quantity of residual polarization electric charge inside the ferroelectric thin film layer, as the quantity of electrically charged up charged by the ferroelectric capacitor.