Semiconductor memory device and method of controlling the same
A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
1. A semiconductor memory device comprising:
a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively;
a plurality of first correcting code generators configured to generate a plurality of first correcting codes to respectively correct errors in a plurality of first data blocks each of which comprises one of the data items and a corresponding detecting code;
a second correcting code generator configured to generate a second correcting code to correct errors in a second data block which comprises the first data blocks;
a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code;
a first corrector configured to correct errors in the first data blocks using the first correcting codes, respectively;
a detector configured to detect, using the detecting codes, errors in the data items corrected by the first corrector, respectively, and generate first error information representing presence/absence of an error in each of the corrected data items; and
a second corrector configured to execute a Chien search for, of the corrected data items, a number of data items containing errors and correct errors using the first error information and the second correcting code,
wherein an error correction capability of the second correcting code is higher than error correction capabilities of the first correcting codes.
2. The device according to claim 1 , wherein the second corrector stops a correction process when the data items corrected by the first corrector contain no error.
3. The device according to claim 1 , wherein the semiconductor memory is a NAND flash memory.