Method to maximize nitrogen concentration at the top surface of gate dielectrics
An integrated circuit having a gate dielectric layer ( 414, 614, 814 ) having an improved nitrogen profile and a method of fabrication. The gate dielectric layer is a graded layer with a significantly higher nitrogen concentration at the electrode surface than near the substrate surface. An amorphous silicon layer ( 406 ) may be deposited prior to nitridation to retain the nitrogen concentration at the top surface ( 416 ). Alternatively, a thin silicon nitride layer ( 610 ) may be deposited after anneal or a wet nitridation process may be performed.
1. A method for fabricating an integrated circuit, comprising the step of:
forming a SiON gate dielectric layer having a graded nitrogen concentration over a substrate; and
forming a polysilicon gate electrode layer over the SiON gate dielectric layer, wherein the SiON gate dielectric layer has a higher nitrogen concentration adjacent to the polysilicon gate electrode layer than adjacent to the substrate, wherein the step of forming the SiON gate dielectric layer comprises the steps of:
forming a base oxide layer over the substrate;
performing a nitridation process on said base oxide layer to form a SiON layer; and
annealing the SiON layer, wherein said annealing step denudes nitrogen from an upper surface of the SiON layer; and
after annealing the SiON layer, depositing a layer of SiN over the SiON layer.
2. The method of claim 1 , wherein said nitridation process incorporates 5-40 atomic % of nitrogen into the base oxide layer.
3. The method of claim 1 , wherein said annealing step occurs under oxidizing conditions with a partial pressure of oxygen of 1-30 Torr.
4. A method for fabricating an integrated circuit, comprising the step of:
forming a SiON gate dielectric layer having a graded nitrogen concentration over a substrate; and
forming a polysilicon gate electrode layer over the SiON gate dielectric layer, wherein the SiON gate dielectric layer has a higher nitrogen concentration near the polysilicon gate electrode layer than near the substrate, wherein the step of forming the SiON gate dielectric layer comprises the steps of:
forming a base oxide layer over the substrate; and
performing a wet nitridation process;
and wherein the step of forming the SiON gate dielectric layer further comprises performing the following steps prior to performing the wet nitridation process:
performing a nitridation process on said base oxide layer to form a SiON layer; and
annealing the SiON layer, wherein said annealing step denudes nitrogen from an upper surface of the SiON layer.
5. The method of claim 4 , wherein the step of performing the wet nitridation process wet reagent selected from the group consisting of aqueous solutions of hydrazine, phenylhydrazine, hydralazine, hydrazone, amines, acid amides, nitro-aromatics, and nitriles.
6. The method of claim 4 , wherein the wet reagent is provided in tetrahydrofuran.
7. A method of fabricating an integrated circuit, comprising the steps of:
forming a SiON gate dielectric layer having a higher concentration of nitrogen at a gate electrode interface than at a substrate interface by:
forming a base oxide layer;
converting the base oxide layer to a SiON layer;
depositing a layer of silicon nitride over the SiON layer after annealing the SiON layer; and
annealing the SiON layer; and
depositing a polysilicon gate material over the SiON gate dielectric layer.
8. The method of claim 7 , wherein the step of depositing a layer of silicon nitride and the step of depositing the polysilicon gate material are performed in situ, sequentially, and without an air break in between.