IP Library Granted Patent US 8,207,029
Granted Patent B2
US 8,207,029 · App. 12/630,592 · Granted Jun 26, 2012

Method for manufacturing semiconductor device

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,207,029
App. No.
12/630,592
Granted
Jun 26, 2012
Kind
B2
Abstract

A method for manufacturing a semiconductor device includes: forming a stacked body of a dielectric layer including a silicon oxide and a conductive layer including silicon above a substrate; and forming a hole penetrating through the dielectric layer and the conductive layer in the stacked body, the forming the hole including: forming a first mask layer including a silicon oxide above the stacked body; etching the conductive layer while using the first mask layer as a mask; and forming a second mask layer having more silicon content than the dielectric layer above the first mask layer to etch the dielectric layer while using the second mask layer as a mask.

Claims (36)

1. A method for manufacturing a semiconductor device, comprising:

forming a stacked body of a dielectric layer including a silicon oxide and a conductive layer including silicon above a substrate; and

forming a hole penetrating through the dielectric layer and the conductive layer in the stacked body,

the forming the hole including:

forming a first mask layer including a silicon oxide above the stacked body;

etching the conductive layer while using the first mask layer as a mask; and

forming a second mask layer having more silicon content than the dielectric layer above the first mask layer to etch the dielectric layer while using the second mask layer as a mask,

wherein a plurality of the dielectric layers and a plurality of the conductive layers are alternately stacked to form the stacked body,

etching each of the conductive layers while commonly using the first mask layer formed above the stacked body before etching the dielectric layers and the conductive layers and etching each of the dielectric layers after forming the second mask layer above the first mask layer are alternately repeated to form the hole in the stacked body and

forming a dielectric film including a charge storage layer on side wall of the hole after forming the hole; and

providing a semiconductor layer in the hole after forming the dielectric film.

2. The method according to claim 1 , wherein the first mask layer is made thicker than the second mask layer.

3. The method according to claim 1 , wherein thickness of the second mask layer is made not more than thickness of one layer of the conductive layers.

4. The method according to claim 1 , wherein the second mask layer is formed each time before etching each of the dielectric layers.

5. The method according to claim 1 , wherein the first mask layer is formed thick enough to remain when etching lowermost layer of the conductive layers.

6. The method according to claim 1 further comprising forming a silicon nitride layer on the stacked body before forming the first mask layer, wherein the first mask layer is formed on the silicon nitride layer.

7. The method according to claim 1 , wherein the first mask layer includes a first silicon oxide layer and a second silicon oxide layer of which materials are different from each other.

8. The method according to claim 1 , wherein the second mask layer includes SiC.

9. The method according to claim 1 , wherein the second mask layer includes SiN.

10. The method according to claim 1 ,

wherein the second mask layer is formed by plasma CVD (chemical vapor deposition).

11. The method according to claim 10 , wherein the second mask layer is also formed on side wall of the hole in forming the hole.

12. The method according to claim 10 , wherein source gas during the plasma CVD includes SiCl 4 .

13. The method according to claim 12 , wherein the source gas further includes hydrogen (H).

14. The method according to claim 10 , wherein, during the plasma CVD, a substrate above which the stacked body is formed is held at a holding section in a chamber in which plasma is generated and the holding section is grounded.

15. The method according to claim 1 , wherein, during etching of the conductive layer and during etching of the dielectric layer, a substrate above which the stacked body is formed is held at a holding section in a chamber in which plasma is generated and power is applied to the holding section.

16. The method according to claim 1 , wherein etching of the conductive layer, formation of the second mask layer, and etching of the dielectric layer are performed continuously in the same chamber under a reduced-pressure atmosphere.

17. The method according to claim 1 , wherein the forming the dielectric film includes:

forming a first dielectric film on side wall of the hole;

forming the charge storage layer inside the first dielectric film; and

forming a second dielectric film inside the charge storage layer.

18. The method according to claim 1 further comprising:

forming a selection gate above the stacked body after providing the semiconductor layer in the hole;

forming a hole for a selection transistor reaching upper end of the semiconductor layer in the selection gate;

forming a gate dielectric film on side wall of the hole for the selection transistor; and

providing a semiconductor layer for the selection transistor in the hole for the selection transistor after forming the gate dielectric film.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2009
From: ISHIKAWA, MASAO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 023606/0476 →
Priority Claims (1)
JP 2009-021960 · Feb 2, 2009 · national
Continuity (1)
Related Publication 20100197129A1 · Aug 5, 2010