Image sensor with integration time compensation

1. A photosensor chip comprising:

a first set of photosensors comprising an edge pixel and an interior pixel; and,

a control portion for accepting a first external integration signal, said first external integration signal causing an edge pixel integration signal and an interior pixel integration signal for said first set of photosensors, said control portion comprising:

a first signal adjuster effectively altering said first external integration signal to cause said edge pixel integration signal and said interior pixel integration signal for said first set of photosensors said first signal adjuster accepts an edge pixel datum instructing said first signal adjuster to cause said edge pixel integration signal to be different from said first external integration signal by a predetermined edge pixel duration, said predetermined edge pixel duration being related to said edge pixel datum, and said first signal adjuster accepts an interior pixel datum instructing said first signal adjuster to cause said interior pixel integration signal to be different from said first external integration signal by a predetermined interior pixel duration, said predetermined interior pixel duration being related to said interior pixel datum.

2. The photosensor chip according to claim 1 , wherein said first signal adjuster effectively causes said edge pixel integration signal and said interior pixel integration signal to be different from said first external integration signal by a predetermined edge pixel duration and a predetermined interior pixel duration, respectively.

3. The photosensor chip according to claim 1 , wherein said first external integration signal comprises a duration, said duration comprising a plurality of clock cycles, said control portion further comprising:

a first counter outputting a multiplier value upon reaching a predetermined number of said plurality of clock cycles, said multiplier value is proportional to said predetermined number and causes said first signal adjuster to effectively alter said first external integration signal to cause said edge pixel integration signal and said interior pixel integration signal for said first set of photosensors, wherein said edge pixel integration signal and said interior pixel integration signal are proportional to said multiplier value.

4. The photosensor chip according to claim 3 , said control portion further comprising:

a clock generator receiving said edge pixel integration signal and said interior pixel integration signal for said first set of photosensors and effectively using said edge and interior pixel integration signals to cause respective first edge transfer gate signals and first interior transfer gate signals, to further cause respective first edge fat zero clock signals and first interior fat zero clock signals, and to yet further cause respective first edge muxing signals and first interior muxing signals for said photosensor chip.

5. The photosensor chip according to claim 1 , said control portion further comprising:

a clock generator receiving said edge pixel integration signal and said interior pixel integration signal for said first set of photosensors and effectively using said edge and interior pixel integration signals to cause respective first edge transfer gate signals and first interior transfer gate signals, to further cause respective first edge fat zero clock signals and first interior fat zero clock signals, and to yet further cause respective first edge muxing signals and first interior muxing signals for said photosensor chip.

6. The photosensor chip according to claim 1 further comprising:

a second set of photosensors comprising an edge pixel and an interior pixel; and,

said control portion accepting a second external integration signal, said second external integration signal causing an edge pixel integration signal and an interior pixel integration signal for said second set of photosensors, said control portion further comprising:

a second signal adjuster effectively altering said second external integration signal to cause said edge pixel integration signal and said interior pixel integration signal for said second set of photosensors.

7. The photosensor chip according to claim 6 , wherein said first set of photosensors is sensitive to a first color and said second set of photosensors is sensitive to a second color.

8. A photosensitive apparatus comprising:

a plurality of photosensor chips, each photosensor chip comprising:

a first set of photosensors comprising an edge pixel and an interior pixel; and,

a control portion for accepting a first external integration signal, said first external integration signal causing an edge pixel integration signal and an interior pixel integration signal for said first set of photosensors, said control portion comprising:

a first signal adjuster effectively altering said first external integration signal to cause said edge pixel integration signal and said interior pixel integration signal for said first set of photosensors; and,

a first common line for applying said first external integration signal to each of said plurality of photosensor chips a first counter outputting a multiplier value upon reaching a predetermined number of said plurality of clock cycles, said multiplier value is proportional to said predetermined number and causes said first signal adjuster to effectively alter said first external integration signal to cause said edge pixel integration signal and said interior pixel integration signal for said first set of photosensors, wherein said edge pixel integration signal and said interior pixel integration signal are proportional to said multiplier value.

9. The photosensitive apparatus according to claim 8 , said control portion of each photosensor chip further comprising:

a clock generator receiving said edge pixel integration signal and said interior pixel integration signal for said first set of photosensors and effectively using said edge and interior pixel integration signals to respective first edge transfer gate signals and first interior transfer gate signals, to further cause respective first edge fat zero clock signals and first interior fat zero clock signals, and to yet further cause respective first edge muxing signals and first interior muxing signals for said photosensor chip.

10. The photosensitive apparatus of claim 8 further comprising:

a second common line for applying a second external integration signal to each of said plurality of photosensor chips; and,

each photosensor chip further comprising:

a second set of photosensors comprising an edge pixel and an interior pixel; and,

said control portion accepting said second external integration signal, said second external integration signal causing an edge pixel integration time and an interior pixel integration time for said second set of photosensors, said control portion further comprising:

a second signal adjuster effectively altering said second external integration signal to cause said edge pixel integration signal and said interior pixel integration signal for said second set of photosensors.

11. The photosensitive apparatus of claim 10 , wherein, for each photosensor chip, said first set of photosensors is sensitive to a first color and said second set of photosensors is sensitive to a second color.