Power semiconductor device

1. A power semiconductor device comprising:

a high voltage unit that provides a high voltage control signal so that a high voltage is output;

a low voltage unit that provides a low voltage control signal so that a ground voltage is output, and is spaced apart from the high voltage unit;

a charge enable unit that is electrically connected to the low voltage unit and charges a bootstrap capacitor for supplying power to the high voltage unit when the high voltage is output, when the ground voltage is output; and

a high voltage cut-off unit that cuts off the high voltage when the high voltage is output so that the high voltage is not applied to the charge enable unit, and comprises a first terminal electrically connected to the charge enable unit and a second terminal electrically connected to the high voltage unit.

2. The power semiconductor device of claim 1 , wherein the charge enable unit comprises a diode.

3. The power semiconductor device of claim 2 , wherein the diode comprises an anode and a cathode,

wherein the anode is electrically connected to a driving power source, and

wherein the cathode is electrically connected to the first terminal of the high voltage cut-off unit by a conductive layer.

4. The power semiconductor device of claim 2 , wherein the charge enable unit comprises:

an n-type semiconductor layer formed on a p-type semiconductor substrate;

an insulating layer formed on the n-type semiconductor layer; and

a p-type conductive layer and an n-type conductive layer formed on the insulating layer in a junction.

5. The power semiconductor device of claim 4 , wherein a first isolation region is formed in the n-type semiconductor layer, and

wherein the charge enable unit and the low voltage unit are isolated from each other by the first isolation region.

6. The power semiconductor device of claim 4 , wherein the p-type conductive layer is insulated from the n-type semiconductor layer by the insulating layer.

7. The power semiconductor device of claim 4 , wherein a cathode contact is formed on the n-type conductive layer,

wherein a source region having a high concentration, on which the first terminal of the high voltage cut-off unit is formed, is formed on the n-type semiconductor layer, and

wherein the cathode contact is electrically connected to the source region.

8. The power semiconductor device of claim 4 , wherein the p-type conductive layer and the n-type conductive layer are formed of polysilicon.

9. The power semiconductor device of claim 1 , wherein the charge enable unit comprises a PNP transistor.

10. The power semiconductor device of claim 9 , wherein the PNP transistor comprises an emitter, a base, and a collector,

wherein the emitter is electrically connected to a driving power source, and

wherein the base and the collector are electrically connected to the first terminal of the high voltage cut-off unit.

11. The power semiconductor device of claim 9 , wherein the charge enable unit comprises:

an n-type semiconductor layer formed on a p-type semiconductor substrate;

a p-type well formed in the n-type semiconductor layer;

an n-type well formed in the p-type well; and

a p-type body formed in the n-type well.

12. The power semiconductor device of claim 11 , wherein the p-type well comprises a p-type under layer formed under the n-type well and a p-type side well formed at a side of the n-type well, and

wherein the p-type under layer has a higher concentration than that of the p-type side well.

13. The power semiconductor device of claim 11 , wherein the charge enable unit further comprises an n-type under layer formed between the p-type semiconductor substrate and the p-type well.

14. The power semiconductor device of claim 13 , wherein the n-type under layer has a higher concentration than that of the p-type well and the n-type well.

15. The power semiconductor device of claim 11 , further comprising:

an emitter region having a high concentration that is formed in the p-type body;

a base region having a high concentration that is formed in the n-type well;

a collector region having a high concentration that is formed in the p-type well;

a base contact formed on the base region; and

a collector contact formed on the collector region,

wherein a source region having a high concentration, on which the first terminal of the high voltage cut-off unit is formed, is formed on the n-type semiconductor layer, and

wherein the base contact and the collector contact are electrically connected to the source region.

16. The power semiconductor device of claim 1 , wherein the high voltage cut-off unit comprises an n-channel junction field effect transistor (JFET), and

wherein the first and second terminals of the high voltage cut-off unit are a source and a drain of the n-channel JFET, respectively.

17. The power semiconductor device of claim 16 , wherein the high voltage cut-off unit comprises:

an n-type semiconductor layer formed on a p-type semiconductor substrate; and

a p-type field forming layer formed in the n-type semiconductor layer.

18. The power semiconductor device of claim 17 , further comprising:

a source region having a high concentration that is formed in the n-type semiconductor layer;

a source contact formed on the source region;

a drain region having a high concentration that is formed in the n-type semiconductor layer;

a drain contact formed on the drain region;

a gate region having a high concentration that is formed in the p-type field forming layer; and

a gate contact formed on the gate region,

wherein the gate region is closer to the source region than to the drain region.

19. The power semiconductor device of claim 18 , wherein the high voltage cut-off unit further comprises a p-type well that partially overlaps the p-type field forming layer under the gate region and has a greater thickness than that of the p-type field forming layer.

20. The power semiconductor device of claim 18 , wherein the high voltage cut-off unit further comprises an n-type buried layer formed between the n-type semiconductor layer and the p-type semiconductor substrate and below the drain region, and

wherein the n-type buried layer has a higher concentration than that of the p-type field forming layer.

21. The power semiconductor device of claim 18 , wherein the gate contact of the n-channel JFET is grounded.

22. The power semiconductor device of claim 17 , wherein the high voltage cut-off unit and the high voltage unit are isolated from each other by a second isolation region formed in the n-type semiconductor layer.

23. The power semiconductor device of claim 1 , wherein the high voltage unit, the low voltage unit, the charge enable unit, and the high voltage cut-off unit are formed on a p-type semiconductor substrate,

wherein the charge enable unit and the high voltage cut-off unit are formed on an n-type semiconductor layer formed on the p-type semiconductor substrate, and

wherein the charge enable unit and the high voltage cut-off unit are directly connected to each other without a separate isolation region, on the n-type semiconductor layer.