IP Library Granted Patent US 8,222,718
Granted Patent B2
US 8,222,718 · App. 12/366,039 · Granted Jul 17, 2012

Semiconductor die package and method for making the same

Assignee: Fairchild Semiconductor Corporation
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Quick Facts
Patent No.
US 8,222,718
App. No.
12/366,039
Granted
Jul 17, 2012
Kind
B2
Abstract

A semiconductor die package. The semiconductor die package includes a premolded clip structure assembly having a clip structure, a semiconductor die attached to the clip structure, and a first molding material covering at least a portion of the clip structure and the semiconductor die. The semiconductor die package also includes a leadframe structure having a die attach pad, where the leadframe structure is attached to premolded clip structure assembly.

Claims (26)

1. A semiconductor die package comprising:

a premolded clip structure assembly comprising a clip structure, a semiconductor die attached to the clip structure, and a first molding material covering at least a portion of the clip structure and covering at least a portion of an edge of the semiconductor die;

a leadframe structure comprising a die attach pad, wherein the leadframe structure is attached to premolded clip structure assembly; and

a second molding material covering at least a portion of the leadframe structure and the premolded clip structure assembly; and

wherein the first molding material contacts the second molding material, and wherein an interface exists between the first and second molding materials.

2. The semiconductor die package of claim 1 further comprising a conductive adhesive between the leadframe structure and the premolded clip structure assembly.

3. The semiconductor die package of claim 2 wherein the conductive adhesive is a first conductive adhesive and wherein the premolded clip structure assembly comprises a second conductive adhesive between the clip structure and the semiconductor die.

4. The semiconductor die package of claim 3 wherein the semiconductor die comprises a power semiconductor die comprising a power MOSFET.

5. The semiconductor die package of claim 3 , wherein the first conductive adhesive comprises a first solder with a first melting temperature, and wherein the second conductive adhesive comprises a second solder with a second melting temperature that is greater than the first melting temperature.

6. The semiconductor die package of claim 1 wherein the premolded clip structure assembly comprises a first surface and a second surface opposite the first surface, wherein the first surface comprises a first molding material surface and a surface of the semiconductor die.

7. The semiconductor die package of claim 1 wherein the first molding material covers all edges of the semiconductor die.

8. The semiconductor die package of claim 1 wherein the semiconductor die is a first semiconductor die and the semiconductor die package comprises a second semiconductor die, wherein all of edges of the second semiconductor die are covered by the first molding material.

9. The semiconductor die package of claim 1 wherein the semiconductor die comprises a drain region, and wherein the clip structure is electrically coupled to the drain region of the semiconductor die.

10. The semiconductor die package of claim 9 wherein the first molding material covers all edges of the semiconductor die.

11. A semiconductor die package comprising:

a leadframe structure comprising a leadframe structure surface;

a semiconductor die attached to the leadframe structure, wherein the semiconductor die comprises a first surface comprising an input region and a second surface comprising an output region;

a molding material covering at least a portion of an edge of the semiconductor die and covering at least a portion of the leadframe structure, wherein the molding material exposes the second surface of the semiconductor die and also exposes the leadframe structure surface;

a metallic housing structure comprising a major portion and a first leg extending from the major portion and a second leg extending from the major portion opposite the first leg, wherein the metallic housing including the major portion, the first leg and the second leg is electrically and mechanically coupled to the output region at the second surface of the semiconductor die; and

a conductive adhesive coupling the major portion of the metallic housing structure and the second surface of the semiconductor die.

12. The semiconductor die package of claim 11 wherein the metallic housing structure comprises copper.

13. The semiconductor die package of claim 11 wherein the semiconductor die comprises a power MOSFET.

14. The semiconductor die package of claim 11 wherein molding material is spaced from the first and second legs.

15. The semiconductor die package of claim 11 wherein the metallic housing structure is a single unitary body.

16. The semiconductor die package of claim 11 wherein the major portion, the first leg and the second leg comprise copper.

17. The semiconductor die package of claim 11 further comprising a conductive adhesive, wherein the major portion is coupled to the output region using the conductive adhesive.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2012
From: JEREZA, ARMAND VINCENT C.; CALO, PAUL ARMAND; CRUZ, ERWIN VICTOR R.
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 028224/0395 →
Continuity (1)
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