Low power antifuse sensing scheme with improved reliability
Generally, a method and circuit for improving the retention and reliability of unprogrammed anti-fuse memory cells. This is achieved by minimizing the tunneling current through the unprogrammed anti-fuse memory cells which can cause eventual gate oxide breakdown. The amount of time a read voltage is applied to the anti-fuse memory cells is reduced by pulsing a read voltage applied to a wordline connected to the unprogrammed anti-fuse memory cells, thereby reducing the tunneling current. Further tunneling current can be reduced by decoupling the unprogrammed anti-fuse memory cells from a sense amplifier that can drive the corresponding bitline to VSS.
1. A method for reading programmed and unprogrammed anti-fuse memory cells comprising:
i) driving a selected wordline connected to an anti-fuse device of an anti-fuse memory cell to a read voltage;
ii) charging a bitline electrically coupled to the anti-fuse device in response to the selected wordline at the read voltage;
iii) decoupling the anti-fuse device from the bitline; and
iv) enabling a sense amplifier to sense a voltage level of the bitline.
2. The method of claim 1 , further including precharging the bitline and a reference bitline to a first voltage supply prior to driving the selected wordline.
3. The method of claim 2 , wherein charging includes adding a reference charge to the reference bitline.
4. The method of claim 2 , wherein driving includes driving the bitline to one of the first voltage supply and a second voltage supply, and driving the reference bitline to the other of the first voltage supply and the second voltage supply.
5. The method of claim 1 , wherein decoupling includes decoupling the bitline from a sense node of the sense amplifier.
6. The method of claim 5 , wherein decoupling the bitline includes turning off an isolation transistor between the bitline and the sense node of the sense amplifier.
7. The method of claim 6 , wherein the selected wordline is disabled after decoupling.
8. The method of claim 1 , wherein the anti-fuse memory cell includes an access transistor connected between the bitline and the anti-fuse device, and decoupling includes turning off the access transistor.
9. The method of claim 1 , wherein driving includes pulsing the selected wordline with a wordline pulsing scheme.
10. The method of claim 9 , wherein the wordline pulsing scheme includes a single pulse.
11. The method of claim 9 , wherein the wordline pulsing scheme includes wordline pulses having fixed width pulses.
12. The method of claim 9 , wherein the wordline pulsing scheme includes wordline pulses having variable width pulses.
13. The method of claim 9 , wherein the wordline pulsing scheme includes wordline pulses having partial pulses.
14. The method of claim 9 , wherein pulsing of the wordline ends after decoupling.
15. A method for reading programmed and unprogrammed anti-fuse memory cells comprising:
i) pulsing a selected wordline connected to an anti-fuse device of an anti-fuse memory cell between a first voltage and a second voltage;
ii) charging a bitline electrically coupled to the anti-fuse device in response to the selected wordline being pulsed; and,
iii) enabling a sense amplifier to sense a voltage level of the bitline.
16. The method of claim 15 , wherein the selected wordline has pulses with fixed widths.
17. The method of claim 15 , wherein the selected wordline has pulses with variable widths.
18. The method of claim 15 , wherein the selected wordline has pulses that rise to the first voltage and fall to a third voltage between the first voltage and the second voltage.
19. The method of claim 15 , further including decoupling the anti-fuse device before sensing.
20. The method of claim 19 , wherein pulsing of the wordline ends after decoupling.
21. The method of claim 19 , wherein decoupling includes decoupling the bitline from a sense node of the sense amplifier.
22. The method of claim 19 , wherein the anti-fuse memory cell includes an access transistor connected between the bitline and the anti-fuse device, and decoupling includes turning off the access transistor.
23. An anti-fuse memory comprising:
anti-fuse memory cells connected to wordlines and bitlines;
wordline drivers for driving the wordlines with at least one voltage level;
a voltage circuit for providing the at least one voltage level; and,
a pulse control circuit for enabling and disabling the wordline drivers in a read operation to provide the at least one voltage level in accordance with a pulsing scheme.
24. The anti-fuse memory of claim 23 , wherein the pulse control circuit enables and disables the wordline drivers at fixed intervals to provide pulses of a fixed width.
25. The anti-fuse memory of claim 24 , wherein the voltage circuit provides an intermediate voltage, and the wordline drivers are disabled to provide the intermediate voltage, the intermediate voltage being greater than VSS.
26. The anti-fuse memory of claim 23 , wherein the pulse control circuit enables and disables the wordline drivers at variable intervals to provide pulses of a variable width.