Resistance change memory device

1. A resistance change memory device comprising:

memory cells each comprising two transistors connected in parallel between a first node and a connecting node and a variable resistance element comprising a first end connected to the connecting node and at least two states different in resistance, the memory cells being in a matrix comprising a first axis and a second axis; and

bit lines, wherein

the first node of each memory cell of the memory cells and a second node which is an second end of the variable resistance element of the memory cell are connected to different bit lines among the bit lines,

the first node of a first memory cell of the memory cells and the first node of a second memory cell next to the first memory cell on a first side along the second axis are connected to the same bit line, and

the second node of the first memory cell and the second node of a third memory cell next to the first memory cell on a second side along the second axis are connected to the same bit line.

2. The device of claim 1 , wherein the bit lines on the first side along the second axis from one access-target memory cell for writing or reading are at a first potential, and the bit lines on the second side along the second axis from the access-target memory cell are at a second potential, while at least one of writing to the memory cell and reading from the memory cell.

3. The device of claim 1 , wherein the bit lines comprise a first group of bit lines shared by the memory cells along the second axis, and a second group of bit lines not shared by the memory cells along the second axis.

4. The device of claim 3 , wherein the bit lines on the first side along the second axis from one access-target memory cell for writing or reading are at a first potential, and the bit lines on the second side along the second axis from the access-target memory cell are at a second potential, among bit lines between two bit lines of the second group of bit lines, while at least one of writing to the memory cell and reading from the memory cell.

5. The device of claim 2 , wherein the transistors of the access-target memory cell are turned on after the bit lines are set to a given potential before the transistors of one access target memory cell are turned on, while writing to the memory cells and reading from the memory cells.

6. The device of claim 2 , further comprising:

a current source circuit connected through gate circuits to a first end of each of the bit lines and configured to cause at least one of the bit lines to be at the first potential; and

a current sink circuit connected through gate circuits to a second end of each of the bit lines and configured to cause at least one of the bit lines to be at the second potential.

7. The device of claim 6 , further comprising a sense amplifier connected through the gate circuits to the first end of the bit lines.

8. The device of claim 2 , wherein

the device further comprises a first current source circuit and a first current sink circuit connected through gate circuits to a first end of each of the bit lines, and a second current source circuit and a second current sink circuit connected through gate circuits to a second end of each of the bit lines,

the first and second current source circuits are configured to cause at least one of the bit lines to be at the first potential, and

the first and second current sink circuits are configured to cause at least one of the bit lines to be at the second potential.

9. The device of claim 8 , further comprising:

a first sense amplifier connected in parallel to the first current source circuit; and

a second sense amplifier connected in parallel to the second current source circuit.