Manufacturing method of semiconductor device, semiconductor device, and electronic device
View Patent ↗An embrittlement layer is formed in a single crystal semiconductor substrate having a (110) plane as a main surface by irradiation of the main surface with ions, and an insulating layer is formed over the main surface of the single crystal semiconductor substrate. The insulating layer and a substrate having an insulating surface are bonded, and the single crystal semiconductor substrate is separated along the embrittlement layer to provide a single crystal semiconductor layer having the (110) plane as a main surface over the substrate having the insulating surface. Then, an n-channel transistor and a p-channel transistor are formed so as to each have a <110> axis of the single crystal semiconductor layer in a channel length direction.
1. A manufacturing method of a semiconductor device, comprising the steps of:
forming an embrittlement layer in a single crystal semiconductor substrate having a (110) plane as a main surface by irradiation of the main surface with ions;
forming an insulating layer over the main surface of the single crystal semiconductor substrate;
bonding the insulating layer and a substrate having an insulating surface;
separating the single crystal semiconductor substrate along the embrittlement layer to provide a single crystal semiconductor layer having the (110) plane as a main surface over the substrate having the insulating surface; and
forming an n-channel transistor and a p-channel transistor to each have a <110> axis of the single crystal semiconductor layer in a channel length direction.
2. The manufacturing method of a semiconductor device according to claim 1 , wherein the insulating layer includes a silicon oxide film formed by a chemical vapor deposition method using an organosilane gas.
3. The manufacturing method of a semiconductor device according to claim 1 , wherein plasma treatment is performed on the main surface of the single crystal semiconductor substrate.
4. The manufacturing method of a semiconductor device according to claim 1 , wherein the ions include any of H + , H 2 + , and H 3 + .
5. The manufacturing method of a semiconductor device according to claim 1 , wherein the n-channel transistor and the p-channel transistor are formed so as to satisfy a relation:
W n /L n :W p /L p =1 :x (0.8≦ x≦ 2),
where L n is a channel length of the n-channel transistor, W n is a channel width of the n-channel transistor, L p is a channel length of the p-channel transistor, and W p is a channel width of the p-channel transistor.
6. A manufacturing method of a semiconductor device, comprising the steps of:
forming an embrittlement layer in a single crystal semiconductor substrate having a (110) plane as a main surface by irradiation of the main surface with ions;
forming an insulating layer over a substrate having an insulating surface;
bonding the insulating layer and the single crystal semiconductor substrate;
separating the single crystal semiconductor substrate along the embrittlement layer to provide a single crystal semiconductor layer having the (110) plane as a main surface over the substrate having the insulating surface; and
forming an n-channel transistor and a p-channel transistor to each have a <110> axis of the single crystal semiconductor layer in a channel length direction.
7. The manufacturing method of a semiconductor device according to claim 6 , wherein the insulating layer includes a silicon oxide film formed by a chemical vapor deposition method using an organosilane gas.
8. The manufacturing method of a semiconductor device according to claim 6 , wherein plasma treatment is performed on the main surface of the single crystal semiconductor substrate.
9. The manufacturing method of a semiconductor device according to claim 6 , wherein the ions include any of H + , H 2 + , and H 3 + .
10. The manufacturing method of a semiconductor device according to claim 6 , wherein the n-channel transistor and the p-channel transistor are formed so as to satisfy a relation:
W n /L n :W p /L p =1 :x (0.8≦ x≦ 2),
where L n is a channel length of the n-channel transistor, W n is a channel width of the n-channel transistor, L p is a channel length of the p-channel transistor, and W p is a channel width of the p-channel transistor.
11. A manufacturing method of a semiconductor device, comprising the steps of:
forming an embrittlement layer in a single crystal semiconductor substrate having a (110) plane as a main surface by irradiation of the main surface with ions;
forming a first insulating layer over a substrate having an insulating surface;
forming a second insulating layer over the main surface of the single crystal semiconductor substrate;
bonding the first insulating layer and the second insulating layer;
separating the single crystal semiconductor substrate along the embrittlement layer to provide a single crystal semiconductor layer having the (110) plane as a main surface over the substrate having the insulating surface; and
forming an n-channel transistor and a p-channel transistor to each have a <110> axis of the single crystal semiconductor layer in a channel length direction.
12. The manufacturing method of a semiconductor device according to claim 11 , wherein the first insulating layer or the second insulating layer includes a silicon oxide film formed by a chemical vapor deposition method using an organosilane gas.
13. The manufacturing method of a semiconductor device according to claim 11 ,
wherein the first insulating layer includes a silicon oxide film, and
wherein the second insulating layer includes any of a silicon oxide film, a silicon oxynitride film, and a silicon nitride oxide film.
14. The manufacturing method of a semiconductor device according to claim 11 ,
wherein the first insulating layer has a stacked structure of a silicon nitride film and a silicon oxide film, and
wherein the second insulating layer includes a silicon oxide film.
15. The manufacturing method of a semiconductor device according to claim 11 , wherein plasma treatment is performed on the main surface of the single crystal semiconductor substrate.
16. The manufacturing method of a semiconductor device according to claim 11 , wherein the ions include any of H + , H 2 + , and H 3 + .
17. The manufacturing method of a semiconductor device according to claim 11 , wherein the n-channel transistor and the p-channel transistor are formed so as to satisfy a relation:
W n /L n :W p /L p =1 :x (0.8≦ x≦ 2),
where L n is a channel length of the n-channel transistor, W n is a channel width of the n-channel transistor, L p is a channel length of the p-channel transistor, and W p is a channel width of the p-channel transistor.
18. A manufacturing method of a semiconductor device, comprising the steps of:
forming a first insulating layer over a main surface of a (110) plane of a single crystal semiconductor substrate;
forming an embrittlement layer in the single crystal semiconductor substrate by irradiation of the first insulating layer with ions;
forming a second insulating layer over a substrate having an insulating surface;
bonding the second insulating layer and the first insulating layer;
separating the single crystal semiconductor substrate along the embrittlement layer to provide a single crystal semiconductor layer having the (110) plane as a main surface over the substrate having the insulating surface; and
forming an n-channel transistor and a p-channel transistor to each have a <110> axis of the single crystal semiconductor layer in a channel length direction.
19. The manufacturing method of a semiconductor device according to claim 18 , wherein the second insulating layer includes a silicon oxide film formed by a chemical vapor deposition method using an organosilane gas.
20. The manufacturing method of a semiconductor device according to claim 18 , wherein the first insulating layer includes any of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a silicon nitride oxide film.
21. The manufacturing method of a semiconductor device according to claim 18 , wherein the ions include any of H + , H 2 + , and H 3 + .
22. The manufacturing method of a semiconductor device according to claim 18 , wherein the n-channel transistor and the p-channel transistor are formed so as to satisfy a relation:
W n /L n :W p /L p =1 :x (0.8≦ x≦ 2),
where L n is a channel length of the n-channel transistor, W n is a channel width of the n-channel transistor, L p is a channel length of the p-channel transistor, and W p is a channel width of the p-channel transistor.